International Business Machines Corporation

Christine M Yost

Elpida Tzortzatos

Timothy John Slegel

Lisa Cranton Heller

Damian Leo Osisek

Scott Brady Compton

Ute Gaertner

Bruce C Giamei

Steven M Partlow

Christian Borntraeger

Christian Jacobi

Charles Franklin Webb

Peter Jeremy Relson

An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.

Reset dynamic address translation protection instruction

Operating system deactivation of write protection for a storage block is provided absent quiescing of processors in a multi-processor computing environment. The process includes receiving an address translation protection exception interrupt resulting from an attempted write access by a processor to a storage block, and determining by the operating system whether write protection for the storage block is active. Based on write protection for the storage block not being active, the operating system issues an instruction to clear or modify translation lookaside buffer entries of the processor associated with the storage block, absent waiting for an action by another processor of multiple processors of the computing environment, to facilitate write access to the storage block proceeding at the processor.

Operating system deactivation of storage block write protection absent quiescing of processors

A computer-implemented method for switching between a full space and a subspace across multiple address spaces is described. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space and the subspace is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled and switches, by the processor, the context of the multiple spaces based on determining that the new context is different from the existing context.

Access to dynamic address translation across multiple spaces for operational context subspaces

A computer-implemented method for implementing a full space dynamic address translation ('DAT') structure and a subspace DAT structure is provided. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space DAT structure and the subspace DAT structure is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled, and switches, by the processor, the context of the DAT structures based on determining that the new context is different from the existing context.

Operational context subspaces

A method for frame choosing in a computing system during a storage constraint condition is provided. The method includes calculating, with a processor, a use-grouped-threshold, comparing a number of available grouped frames to the calculated use-grouped-threshold, returning a decision to use a grouped frame in an event that the number of the available grouped frames exceeds the calculated use-grouped-threshold and returning a decision to use an above-the-bar frame in an event that the number of the available grouped frames is less than or equal to the calculated use-grouped-threshold.

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Hopewell Jct., NY, United States of America

Christine M Yost