International Business Machines Corporation

Christine M Desnoyers

Douglas James Joseph

Derrick LeRoy Garmire

Francis Alfred Kampf

David B Rolfe

Billy J Knowles

Robert Frederick Stucke

Alan Frederic Benner

Dale E Pontius

Francis A Kampf

Clive A Collins

Daniel Francis Casper

Frank David Ferraiolo

Marten J Halma

Robert S Capowski

Donald G Grice

Antoinette Elaine Herrmann

Peter Kenneth Szwed

Carl Alfred Bender

Clive Allan Collins

Michael Patrick Muhlada

Donna C Myers

William R Milani

Antoinette E Vallone

Vadim M Tsinker

Sheryl M Genco

A program product for a message processing system in which messages are transmitted from source nodes to destination nodes. A transmission flow control technique is disclosed in which the source node optimistically sends control information and a data portion of a message, and wherein a destination node discards the data portion of the message if it is unable to accommodate it. The destination node, however, retains enough of the control information to identify the message to the source node, and when the destination node is subsequently able to accommodate the data portion, the destination node issues a request to the source node to retransmit the data portion of the message. Discarding of one message is followed by discards of sequential messages, until the destination node is able to accommodate the data portions of messages. The flow control technique disclosed herein is used, for example, in an environment where buffers are posted to accommodate messages at the destination node, and is particularly suited for conditions arising in multi-tasking systems where the destination node is generally assumed to be prepared to accommodate data, however, if not prepared, is likely not prepared for long periods of time.

Optimistic transmission flow control including receiver data discards upon inadequate buffering condition

A method for a message processing system in which messages are transmitted from source nodes to destination nodes. A transmission flow control technique is disclosed in which the source node optimistically sends control information and a data portion of a message, and wherein a destination node discards the data portion of the message if it is unable to accommodate it. The destination node, however, retains enough of the control information to identify the message to the source node, and when the destination node is subsequently able to accommodate the data portion, the destination node issues a request to the source node to retransmit the data portion of the message. Discarding of one message is followed by discards of sequential messages, until the destination node is able to accommodate the data portions of messages. The flow control technique disclosed herein is used, for example, in an environment where buffers are posted to accommodate messages at the destination node, and is particularly suited for conditions arising in multi-tasking systems where the destination node is generally assumed to be prepared to accommodate data, however, if not prepared, is likely not prepared for long periods of time.

Flow control system using control information of a message for initiating retransmission of data portion when buffer is available

A system for a message processing system in which messages are transmitted from source nodes to destination nodes. A transmission flow control technique is disclosed in which the source node optimistically sends control information and a data portion of a message, and wherein a destination node discards the data portion of the message if it is unable to accommodate it. The destination node, however, retains enough of the control information to identify the message to the source node, and when the destination node is subsequently able to accommodate the data portion, the destination node issues a request to the source node to retransmit the data portion of the message. Discarding of one message is followed by discards of sequential messages, until the destination node is able to accommodate the data portions of messages. The flow control technique disclosed herein is used, for example, in an environment where buffers are posted to accommodate messages at the destination node, and is particularly suited for conditions arising in multi-tasking systems where the destination node is generally assumed to be prepared to accommodate data, however, if not prepared, is likely not prepared for long periods of time.

System for optimistic transmission flow control including receiver data discards upon inadequate buffering condition

A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.

Synchronous interface for transmitting data in a system of massively parallel processors

A method, system, and associated program code and data structures are provided for a message processing system in which messages are passed from source nodes to destination nodes. Notification of the arrival of the messages at the destination nodes can be effected by programmable source initiated interrupts or destination initiated interrupts. The source initiated interrupts are implemented as set fields embedded in the message packets sent from a source node to a destination node and trigger the requisite interrupt at the destination node upon message arrival. The destination initiated interrupts are implemented as pre-set fields in anticipatory buffers which are allocated at the destination node for incoming messages from the source node. Standard incoming message queue polling, as well as interrupt enabling and disabling functions are also provided, which together allow the system to selectively invoke interrupt or alternative strategies to notify destination nodes of arriving messages.

Source and destination initiated interrupt system for message arrival

Source and destination initiated interrupt method for message arrival

Source and destination initiated interrupts for message arrival

An error message is generated by a hardware element of a distributed computer system, when an error is detected. The error message is then forwarded from the hardware element to one or more designated processing nodes of the distributed computer system. The hardware element includes, for instance, a switch element or a communications adapter adapted to report detected errors.

System of reporting errors by a hardware element of a distributed

Method of reporting errors by a hardware element of a distributed

Self-timed interface for a network of computer processors interconnected

A parallel computer system providing multi-ported intelligent memory is formed of a plurality of nodes or cells interconnected to provide a shared memory with processors of the network and their memory providing the network routing and shared memory. Each of the nodes provides a functional unit with a processor, shared memory, and communication interface. K zipper ports in addition provide a switching function to interconnect the distributed memory and processors providing the shared memory. The resulting multi-ported shared intelligent memory switch can be used to connect (switch) a variety of computer system elements (CSEs) including computers and direct access storage devices (DASDs). The multi-ported intelligent memory shared memory organized into a collection of cells or nodes and is called the hedgehog. Each node comprises a finite computer memory, a processing unit, and communication interface and at least K of the nodes of the device have a zipper port. The computing system element combines the characteristics of a switch with those of a shared memory. In addition, objects in the shared memory can change state without the intervention of computing system elements (CSEs) that are interconnected to the device (CSE and port) which is a hedgehog switch. A zipper and ISA architecture for the chip are described for implementation of the zipper node of the shared memory device.

Parallel computer system providing multi-ported intelligent memory

The sense amplifier registers (SARs) servicing the arrays of a dynamic random access memory (DRAM) located on a semiconductor chip with a processor are all maintained at full power while unaccessed arrays are powered down to conserve power. Accessing circuits for the DRAM permit accessing by the processor of word length segments of each of the SARs independently of one another so that the SARs function as a read/write cache for the processor.

Dynamic random access memory persistent page implemented as processor

A combiner/memory system interconnects a plurality of computer systems using for example the new HIPPI standard link. The combiner system includes it's own internal storage for rapid shared access to all connected computer systems. The combiner/memory system includes a smart switch for reading header information, arbitrating messsages and connecting computers to each other or to the internal shared storage. The system also includes a mechanism for synchronization of cooperating processes.

Multiple computer system with combiner/memory interconnection system

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Pine Bush, NY, United States of America

Christine M Desnoyers