Infineon Technologies Ag

Siemens Aktiengesellschaft

Other

International Business Machines Corporation

Advanced Technology Materials, Inc.

Qimonda Ag

Infineon Technologies North America Corp.

Christine Dehm

Thomas H Baum

Jeffrey F Roeder

Bryan Clark Hendrix

Peter C Van Buskirk

Frank S Hintermaier

Thomas Mikolajick

Marcus Halik

Hagen Klauk

Thomas Peter Haneder

Debra A Desrochers

Stephen K Loh

Wolfgang Hoenlein

Reinhard J Stengl

Günter Schmid

Christopher Carr Parks

Thomas R&ouml;hr

G&uuml;nther Schindler

Carlos Mazure-Espejo

Arkalgud Sitaram

Carlos Mazuré-Espejo

Recai Sezi

Walter Hartner

Georg Braun

Viraj Yashawant Sardesai

Hermann Wendt

Kurt Hoffmann

Heinz Hoenigschmid

Hans-Joerg Timme

Anthony Gene Domenicucci

Thomas Roehr

Heinz H&ouml;nigschmid

Johann Alsmeier

Volker Weinrich

Andreas Walter

Atul Champaklal Ajmera

Erwin Hammerl

Guenther Schindler

George G Gifford

Marcus Kastner

G&uuml;nter Schmid

Elke Fritsch

Renate Bergmann

Carlos Mazur&eacute;

Carlos Mazure

A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.

NOR and NAND memory arrangement of resistive memory elements

A semiconductor circuit configuration has at least one pair of complementary operating field-effect transistors in which each transistor has a gate region, first and second source/drain regions and also a channel region with or made of an organic semiconductor material that is provided in between. It is furthermore provided that the gate regions are formed such that they are electrically coupled to one another via a capacitor configuration.

Semiconductor circuit configuration and semiconductor memory device

The semiconductor memory cell is characterized in that at least one modulation region is provided between a first gate electrode of the gate electrode configuration and the insulation region, and in that the modulation region has or is formed from a material or modulation material having electrical and/or further material properties that can be modulated in a controllable manner between at least two states in such a way that, in accordance with these states of the modulation material or of the modulation region, the channel region can be influenced electromagnetically, in particular for a given electrical potential difference between the first gate electrode and the source/drain regions.

Semiconductor memory cell and semiconductor memory device

A low temperature CVD process for deposition of bismuth-containing ceramic thin films suitable for integration to fabricate ferroelectric memory devices. The bismuth-containing film can be formed using a tris(&#x3b2;-diketonate) bismuth precursor. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.

Low temperature chemical vapor deposition process for forming bismuth-containing ceramic thin films useful in ferroelectric memory devices

A continuous contact hole is formed in an insulation layer that separates a storage capacitor from a switching transistor. All except a section of the contact hole is filled with poly-Si. A conductive, oxidizable interlayer and a conductive oxygen barrier layer are deposited on the Poly-Si in the remaining section of the contact hole such that the interlayer is completely surrounded by the poly-Si of the contact hole, the insulation layer, and the barrier layer.

Contact-making structure for a ferroelectric storage capacitor and method for fabricating the structure

A storage capacitor, in particular a ferroelectric or paraelectric storage capacitor, and an associated contact-making structure are formed in such a way that the storage capacitor has a first electrode layer, a second electrode layer and a dielectric, ferroelectric or paraelectric capacitor intermediate layer. Proceeding from the plane of the surface of the insulation layer, the storage capacitor extends at least partly into the interior of the via contact and is electrically connected to the via contact.

Storage capacitor and associated contact-making structure and a method for fabricating the storage capacitor and the contact-making structure

A semiconductor memory cell has a field-effect transistor device and a ferroelectric storage capacitor. The field-effect transistor device has a channel region that includes or is made of an organic semiconductor material. Besides a first gate electrode of the gate electrode configuration of the field-effect transistor device, an additional selection gate electrode is provided, by way of which the field-effect transistor device can be switched off without influencing the storage dielectric and independently of the first gate electrode.

A low temperature CVD process using a tris (&bgr;-diketonate) bismuth precursor for deposition of bismuth ceramic thin films suitable for integration to fabricate ferroelectric memory devices. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.

The invention provides a semiconductor memory component with random access, also having a structure which is differentiated into memory cells and logic regions and has a lower oxide layer arranged on a silicon substrate and an upper oxide layer arranged on the lower oxide layer, each memory cell comprising at least one transistor in the transition region between silicon substrate and lower oxide layer and a capacitor in the transition region between lower oxide layer and upper oxide layer, which capacitor is connected to the transistor via a contact hole, which is filled with metal, in the lower oxide layer and comprises a ferroelectric arranged between two electrodes, the electrode which is connected to the transistor and adjoins the lower oxide layer having a relatively great thickness, and each logic region comprising at least one transistor in the transition region between silicon substrate and lower oxide layer, which transistor is connected to an electrode on the topside of the upper oxide layer via a contact hole, which is filled with metal, in the lower oxide layer and the upper oxide layer. According to the invention, it is provided that between the capacitors of the memory cells and the contact holes in the logic regions, level compensation between the topology of the memory cells and of the logic regions is created by dummy structures.

Semiconductor storage component with storage cells, logic areas and filling structures

An integrated ferroelectric memory configuration and a method for producing the integrated ferroelectric memory configuration, in which memory cells are arranged using the stacking principle, and both capacitor electrodes, which are located one above the other, of each memory cell are directly electrically connected by means of contact plugs to corresponding source and drain regions of an associated selection transistor in the substrate. Contact plugs for the contact connection to the upper capacitor electrodes are produced from above the configuration.

Ferroelectric memory configuration and a method for producing the configuration

A cleaning process for cleaning CVD units is disclosed. In the cleaning process, alkaline earth metal and/or metal-containing process residues, which form an amorphous film on reactor walls, are removed using a dry etching medium containing free diketones at a greatly reduced pressure and an elevated temperature. In the process, the free diketones react with the alkaline earth metals or metals to form volatile complexes.

Process for cleaning CVD units

A method of producing a ferroelectric semiconductor memory, includes forming a switching transistor on a semiconductor substrate, applying an insulating layer to the switching transistor and then forming a storage capacitor, with electrodes of platinum and a ferroelectric or paraelectric dielectric, on the insulating layer. In order to protect the dielectric from being penetrated by hydrogen during further process steps, a first barrier layer is embedded into the insulating layer and, after completion of the storage capacitor, a second barrier layer, which bonds with the first barrier layer, is deposited.

Method of producing a ferroelectric semiconductor memory

The invention provides a method. In a first step of a method for fabricating a ferroelectric memory configuration, there is provided a substrate having a multiplicity of memory cells. Each of the memory cells has at least one select transistor, at least one short-circuit transistor, and at least one ferroelectric capacitor. The transistors are connected in an electrically conductive manner to a first of the electrodes of the ferroelectric capacitor. In the next step, at least one electrically insulating layer is applied. In the next step, at least one contact hole for connecting a second electrode of the ferroelectric capacitors is produced. Next, contact holes for connecting the short-circuit transistors are produced. Next, the contact holes are filled with electrically conductive material. Next, an electrically conductive layer is applied and patterned, so that the second electrodes of the ferroelectric capacitors are each conductively connected to the short-circuit transistors.

Method for fabricating a ferroelectric memory configuration

Disclosed is a method for producing semiconductor elements including a metal layer ( ) configured on a semiconductor substrate ( ). The inventive method consists of the following steps: a silicon layer ( ) is deposited on a metal layer ( ); an etch mask is applied in order to structure the silicon layer (1%); the silicon layer is selectively etched ( ) using the etch mask ( ); and the metal layer ( ) is structured in an etching process using a selectively etched silicon layer ( ) as a hard mask.

Method of fabricating semiconductor components

A layer configuration includes a material layer and a diffusion barrier which blocks diffusing material components. The barrier is disposed in the vicinity of a layer boundary of the material layer and is formed predominantly in grain boundaries of the material layer. A process for producing a diffusion barrier is also provided.

Layer configuration with a material layer and a diffusion barrier which blocks diffusing material components and process for producing a diffusion barrier

Growing community of inventors

Nürnberg, Germany

Christine Dehm