Spire Manufacturing

Christine Bui

Hai Dau

Lim Hooi Weng

Kothandan Shanmugam

In one embodiment, the present invention includes an interface assembly for a vertical probe contactor. The interface assembly comprises a base board, a mounting board, a depth adjust plate, and an interface apparatus. The depth adjust plate is between the base board and the mounting board, and the interface apparatus is mounted to the mounting board. The interface apparatus is configured to receive the vertical probe contactor through an opening in the base board and a corresponding opening in the depth adjust plate. A thickness of the depth adjust plate defines a vertical distance between a wafer side of the base board and a plurality of probe tips of the vertical probe contactor.

Interface apparatus for semiconductor testing

In one embodiment, the present invention includes an interface apparatus for semiconductor testing. The interface apparatus includes a housing. The housing includes a lower housing substrate and an upper housing substrate. The lower housing substrate has a plurality of apertures arranged according to a fine pitch, and the upper housing substrate has a plurality of apertures arranged according to a coarse pitch. A plurality of wires passes through the plurality of apertures from the lower housing substrate to the upper housing substrate. Each wire has plated conductive ends emanating from opposing sides of the housing. The plurality of apertures of the lower housing substrate corresponds to the plurality of apertures of the upper housing substrate. The interface apparatus transforms a pattern having a course pitch to a pattern having a fine pitch.

Interface apparatus for semiconductor testing and method of manufacturing same

The present invention includes an interface apparatus for semiconductor testing. The interface apparatus comprises a housing substrate and two product substrates. The first product substrate has a first micro-scale conductive pattern and is situated within a first opening of the housing substrate. The second product substrate has a second micro-scale conductive pattern and is situated within a second opening of the housing substrate. The first and the second micro-scale conductive patterns are aligned to a conductive semiconductor wafer pattern using a continuous translucent media having targets corresponding to the conductive semiconductor wafer pattern.

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Gilroy, CA, United States of America

Christine Bui