National Semiconductor Corporation

Eastman-kodak Company

Christina P Phan

Bumha Lee

Shivani Gupta

Willem J Kindt

Brian D Segerstedt

James B Wieser

Marco Cazzaniga

Qiang Luo

Chris Papalias

Eric Staton

Caron Yvonne Thor

Edith Kwong

A CMOS image sensor includes a plurality of pixels arranged column and rows in an array; a column circuit for storing reset values and a value after integration; a correlated double sampler which derives an image signal from the reset and the value after integration; and an anti-eclipse circuit physically separately from the column circuit and electrically connected to one or shared between multiple columns of pixels for restoring corrupted column voltage on a column of pixels.

Method for correcting eclipse or darkle

An oversaturation protection circuit is provided within a CMOS image sensor. A detector is arranged to monitor an output column line that is associated with a pixel to determine whether the pixel is oversaturated after being reset. If the pixel is oversaturated after being reset, the level of the pixel is determined by measuring the difference between a first reference voltage and the integrated voltage of the pixel. If the pixel is not oversaturated after being reset, the level of the pixel is determined by measuring the difference between the voltage of the column line shortly after reset and the integrated voltage of the pixel. A detector may be arranged to provide the result of the comparison of the associated pixel to be used with other pixels within the pixel column that are adjacent to the associated pixel.

CMOS image sensor oversaturation protection circuit

An array of active pixel sensor cells is operated to substantially reduce the gate induced drain leakage (GIDL) current component of the dark current. In addition, the array is tested to determine the number of cells in the array that are bad, and discards the array of active pixel sensor cells when the number of bad cells exceeds a predefined limit.

Method for reducing dark current for an array of active pixel sensor cells

A circuit and method for increasing the dynamic range of CMOS image sensors designed with a thin gate oxide layer. The circuit includes a high voltage supply circuit and a high voltage level shifter circuit. The high voltage supply circuit is configured to supply a voltage to the shifter circuit. The voltage has a voltage level higher than the maximum supply voltage of the associated fabrication process. The shifter circuit is configured to output a high reset signal based on a reset signal generated to reset a pixel circuit of a pixel array. Instead of the reset signal, the high reset signal is coupled to a gate of the reset transistor in the pixel circuit. The high reset signal allows the reset transistor to maintain a gate to source potential less than the maximum supply voltage even when the high reset signal is greater than the maximum supply voltage.

High voltage reset method for increasing the dynamic range of a CMOS image sensor

A high voltage reset circuit with blooming control that increases the dynamic range of a CMOS image sensor and prevents blooming from occurring in output images. The circuit includes a high voltage supply circuit and a high voltage level shifter circuit. The high voltage supply circuit is configured to supply a voltage to the shifter circuit. The voltage has a voltage level higher than the absolute maximum voltage of the associated fabrication process. The shifter circuit is configured to output a high reset signal based on a reset signal generated to reset a pixel circuit of a pixel array. Instead of the reset signal, the high reset signal is coupled to a gate of the reset transistor in the pixel circuit. The high reset signal allows the reset transistor to maintain a gate to source potential less than the absolute maximum voltage even when the high reset signal is greater than the absolute maximum voltage. The high voltage level shifter circuit includes a high voltage inverter arranged to raise the low level of the high reset signal by a predetermined voltage and to control the rising and falling edges of the RESETsignal. This prevents a photodiode in the pixel circuit from becoming forward biased and prevents blooming from occurring within the image sensor.

Blooming control for a CMOS image sensor

A charge-pump circuit generates a constant voltage higher than the available power supply. A feedback path maintains the voltage at a constant level in spite of power supply, temperature and process variations. This charge pump circuit includes a switched capacitor interface arranged to generate a target voltage that is used to activate and deactivate a bypass capacitor interface to maintain the constant voltage. The bypass capacitor interface is configured to complete the feedback path. The feedback helps to ensure that node n1, that is coupled to the output of the charge pump, stays at a constant potential, irrespective of the power supply voltage.

Constant voltage charge-pump circuit with feedback

A method and apparatus for system offset calibration using an overranging ADC is provided. The overranging ADC is configured to convert an analog signal into an intermediary digital signal. The conversion range of the overranging ADC is extended beyond the full dynamic range of the ADC system. The intermediary digital signal has more bits than the digital output signal. A digital fine offset adjustment circuit is configured to provide the digital output signal by digitally subtracting a fine offset from the intermediary digital signal and decoding the intermediary digital signal. The digital output signal has approximately no offset, and has approximately no loss in dynamic range.

Method and apparatus of system offset calibration with overranging ADC

An integrated circuit having at least one segmented array of switches, wherein the root node of each segmented array of switches is a node whose potential varies with time during operation. Each segmented switch array includes switches connected between nodes having a tree structure. The nodes include the root node and additional nodes of at least two different degrees relative to the root node. By providing a segmented array (rather than a non-segmented array) of switches at a node, the total load capacitance (including parasitic capacitance) at the node is reduced in accordance with the invention. In preferred embodiments, the invention is an analog integrated circuit having a first node at which the potential varies rapidly, and a segmented array of switches whose root node is the first node. Another aspect of the invention is a method for designing an integrated circuit to have reduced load capacitance (e.g., load capacitance due to parasitic capacitance) at at least one sensitive node, including the steps of identifying a sensitive node of a preliminary design for the circuit, wherein an array of switches is coupled to the sensitive node; and determining a refined design for the circuit in which the array is replaced by a segmented switch array comprising switches connected between nodes having a tree structure, wherein the nodes include a root node, and the root node is the sensitive node.

Circuit including segmented switch array for capacitive loading reduction

An active pixel sensor cell array including a XDR reset signal generation circuit configured to generate XDR reset signals having user-selected levels, and an XDR reset signal generation circuit for use with such an array. The XDR reset signal generation circuit includes a digital-to-analog converter (DAC) coupled to receive control bits which determine the level and time of assertion of each XDR reset signal, and a level shifting circuit coupled to the output of the DAC. In response to the control bits (typically a sequence of multi-bit words), the circuit asserts a time-varying XDR reset potential. The XDR reset potential's amplitude as function of time (during each integration period) determines the breakpoints of each cell's response curve. The level shifting circuit includes a reference transistor, whose current density matches that of the reset transistors inside the cells, which shifts the potential at the DAC's output upward by an amount equal to the reference transistor's threshold voltage (which matches the threshold voltage of each reset transistor of the cell array or a row of the cell array) to produce the XDR reset potential. To cause the control bits asserted to the DAC to establish breakpoints which in turn cause the analog-to-digital converter (ADC) of the image sensor array to assert (predictably) an expected set of digital output bits in response to each read of a cell exposed to light of known intensity, both the ADC and the DAC operate at the same reference voltage, and the level shifting circuit's reference transistor's biasing matches that of the reset transistors inside the cells.

Method and circuit for setting breakpoints for active pixel sensor cell to achieve piecewise linear transfer function

Operational amplifiers are often used in unity gain configurations where the output is fed back to the input. In the noninverting buffer configuration the output is directly connected to the inverting input and the circuit becomes a voltage follower. In many cases, the input stage includes cascode coupled transistors which isolate the current mirror load from the differentially operated input transistors. Such cascode transistors act to increase gain to reduce noise and to increase the power supply rejection ratio. When cascode coupled transistors are employed the frequency compensation capacitor can be isolated from loading effects on the input stage, thus, further enhancing the value of a cascoded input stage. However, when such an operational amplifier is operated as a unity gain device its transient response can suffer. Negative output transitions can result in circuit ringing following the negative output transient steps. The invention consists of adding constant current transistors in parallel with the first stage current mirror load elements. It has been shown that such constant current transistors remove the ringing problem without degrading any of the desired circuit parameters.

Stabilized transient response of a cascode CMOS amplifier

An additional device is provided in parallel with one of the input devices of a differential pair. A fixed bias voltage, which is slightly less than the midpoint of the swing range of the input voltage to the differential pair, is applied to the gate of the added device. During the positive swing of the input, the added device remains off and does not effect performance. When the input voltage becomes lower than the fixed bias voltage, the added device turns on and conducts all current needed by the current source, leaving the differential input devices off, and eliminating impact ionization in the differential pair.

Growing community of inventors

Milpitas, CA, United States of America

Christina P Phan