International Business Machines Corporation

Other

Christina Marie Boyko

Voya Rista Markovich

Donald Seton Farquhar

John M Lauffer

Joseph Gene Sabia

Kostas I Papathomas

Richard A Schumacher

Michael Joseph Klodowski

Issa S Mahmoud

Joseph Duane Kulesza

Roy Lynn Arldt

Burtran Joe Cayson

James Francis Muska

Philip Chihchau Liu

Richard Michael Kozlowski

Robert Maynard Japp

Richard W Carpenter

Konstantinos I Papathomas

David John Russell

Krystyna Waleria Semkow

Anthony P Ingraham

Raymond Thomas Galasco

Michael Wozniak

Kristen Ann Stauffer

Robert Jeffrey Day

Issa Said Mahmoud, Deceased

Herbert Wegener

Ronnie Charles McHatton

Natalie Barbara Feilchenfeld

William E Wilson

Brian Eugene Curcio

Stephen Joseph Fuerniss

Bernd Karl-Heinz Appelt

James R Loomis

Kathleen Lorraine Covert

Stanley M Albrechta

Carl E Samuelson

Cindy M Reidsema

Francis J Bucek

Darleen Mayo

Craig Neal Johnston

Ricahrd A Schumacher

A method of making an interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the method includes the steps of providing a substrate having at least one plated through hole therein, and positioning a first conductive layer and a second conductive layer over the at least one plated through hole on opposing surfaces of the substrate. The method includes positioning a layer of dielectric material thereon on the first conductive layer. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, and at least a pair of conductive layers that can carry signals, and power.

Method of making and interconnect structure

The present invention teaches a simplified process for fabricating high density printed wiring boards using a semi-additive process. Steps required to achieve this objective include adhering an electroless plated copper commoning layer to a surface roughened dielectric substrate. Subsequently, the commoning layer is photolithographically personalized by covering the commoning layer with a resist and then uncovering predetermined areas of the aforementioned commoning layer. Consequently, the semi-additive method involves electroplating copper onto the uncovered areas of the commoning layer, thereby generating copper features and circuitry. Finally, the semi-additive process requires the stripping of the remaining photoresist, and the unplated electroless copper layer is etched in order to electronically isolate the copper features and circuitry lines.

Process for manufacturing a printed wiring board

A process of removing excess holefill material from a surface of an electronic substrate in which the holefill residue is contacted with a swelling agent followed by planarizing of the surface in the presence of an agent no stronger than a liquid having a pH of about 6 to about 8.

Process of removing holefill residue from a metallic surface of an electronic substrate

An interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the interconnect structure includes a substrate having at least one plated through hole therein, and a first conductive layer sealing the at least one plated through hole. The substrate includes a layer of dielectric material thereon. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, at least a pair of conductive layers that can carry signals, and at least another pair of conductive layers that can carry power, wherein the pair of conductive layers are shielded by the metal layer and the other pair of conductive layers.

Interconnect structure and method of making same

A printed circuit board is produced by patterning a resist layer according to a circuit mask that defines desired circuit paths. The resist pattern layer is formed by removing the resist from the board in the desired circuit paths and a conductive material is plated onto the board in the resist voids defined by the circuit mask so that the height of the conductive material relative to the substrate equals or exceeds the height of the resist layer relative to the substrate. A low-reactive solution is applied over the conductive material and removes a surface portion of the conductive material. As the solution removes the conductive layer, it forms a film barrier and the solution composition changes, both of which substantially inhibits any further removal of the conductive material. Next, the film barrier is removed from the board allowing another film barrier to form stimulating the removal of further conductive material. The removal step is repeated until the conductive material is at a desired height relative to the height of the resist layer. The board is then finished using conventional circuit board fabrication techniques.

Method of producing fine-line circuit boards using chemical polishing

The invention relates to subtractive and additive processes for creating a circuitized cavity in a printed circuit board. Additionally, the invention includes a circuitized cavity and a printed circuit board with a circuitized cavity. The circuitized cavity provides for a variety of advantages over wire bonds.

Printed circuit board with circuitized cavity and methods of producing same

The present invention teaches a simplified process for fabricating high density printed wiring boards using a semi-additive process. A roughened copper foil is laminated to a dielectric substrate. The foil is subsequently removed from the dielectric to create a roughened, irregular surface on the dielectric substrate. Vertical angle through holes and blind holes are formed in the substrate. A uniform copper commoning layer is electrolessly plated to the roughened dielectric substrate and through holes. A photoresist is applied on the surface of the electroless plated layer and irradiated through a mask having printed circuit features. After developing the photoresist the uncovered electroless layer is electrolytically plated to create the final features and circuitry. After stripping the remaining photoresist the unplated electroless copper layer is etched to electronically isolate the copper features and circuitry lines.

The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.

Via fill compositions for direct attach of devices and methods for applying same

Via fill compositions for direct attach of devices and methods of

A solder interconnection uses preferably lead-rich balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a ball limiting metal mask is formed using photoresist. A thin cap layer of preferably pure tin is deposited on a surface of the solder balls using a tin aqueous immersion process.

Interconnect structure for joining a chip to a circuit card

A method for making a printed circuit with a cavity is disclosed. The method comprises the step of laying a sticker sheet on a first, metallized dielectric layer and laying a second, metallized dielectric layer on the sticker sheet. The second metallized dielectric layer and the sticker sheet each have a window which is registered with the other window forming a cavity. Next, a flexible release layer is laid above the second metallized dielectric layer and a thermosetting visco-plastic material is laid on the release layer over the cavity. Next the first and second metallized dielectric layers, sticker sheet, release layer and visco-plastic material are laminated by heat and pressure to cure the sticker sheet and thereby bind the first and second metallized dielectric sheets to each other. During the lamination step, the sticker sheet flows to the perimeter of the cavity. However, the pressure forces the visco-plastic material tightly into the cavity to seal a bottom perimeter of the cavity such that the sticker sheet forms a smooth fillet at the bottom perimeter of the cavity.

Printed circuit board with cavity for circuitization

A method for producing a layer of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of selecting a core material from one of three iron/nickel alloys, namely either (i) 58% Fe/ 42% Ni; (ii) 60% Fe/39% Ni/1% Cu; or (iii) 60% Fe/38.7% Ni/.12% Mn/.07% Si; forming the core material into a panel suitable for an intended application; cleaning the panel in preparation for plating; plating the panel with copper; subjecting the plated panel to heat treatment; and circuitizing the panel as appropriate for the intended application.

Method for producing multi-layer circuit board and resulting article of

A method for filling a hole in a printed wiring board (PWB) and the resultant PWB. During an intermediate stage in fabrication, a PWB comprises a lamination of dielectric sheets with metalizations on various layers and a plated through hole (PTH). A photoimageable material is formed on a surface of the laminate and covers the PTH. The photoimageable material in a region covering the PTH is partially cured by exposure to light. The remainder of the photoimageable material is developed away. Then, the partially cured photoimageable material in the region of the PTH is pressed into the PTH to form a plug. By application of heat during or after the forcing step, the plug is further cured to a hard condition. For some applications, the plug is mechanically abraded to be flush with one or both surfaces of the laminate. The plug can serve as a solder mask or permit another layer of low viscosity photoimageable material to be formed over the laminate such that the hole, now plugged, will not interfere with the formation of such additional layer.

Method for filling holes in printed wiring boards

Ball limiting metal mask and tin enrichment of high melting point solder

A method for producing a layer of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of selecting a core material from one of three iron/nickel alloys, namely either (i) 58% Fe/42% Ni; (ii) 60% Fe/39% Ni/1% Cu; or (iii) 60% Fe/38.7% Ni/0.12% Mn/0.07% Si; forming the core material into a panel suitable for an intended application; cleaning the panel in preparation for plating; plating the panel with copper; subjecting the plated panel to heat treatment; and circuitizing the panel as appropriate for the intended application.

Growing community of inventors

Conklin, NY, United States of America

Christina Marie Boyko