International Business Machines Corporation

Christian Zoellin

Christian Jacobi

Martin Recktenwald

Aditya Nitin Puranik

Jonathan D Bradbury

Anthony Saporito

Aaron Tsai

Timothy John Slegel

Brian William Thompto

Chung-Lung K Shum

Dung Q Nguyen

Donald W Schmidt

Mark S Farrell

Bruce C Giamei

Brian David Barrick

Sheldon Bernard Levenstein

Markus Helms

Nicholas R Orzol

Dan F Greiner

Markus Kaltenbach

Phillip G Williams

Martin Eckert

Jane Helen Bartik

Wilhelm Ernst Haller

Eyal Naor

Nicolas Maeding

Jang-Soo Lee

Ulrich Krauch

David Jon Lee

Sundeep Chadha

Tamas Visegrady

Susan Elizabeth Eisen

Bradly George Frey

Kurt Alan Feiste

Steven J Battle

Debapriya Chatterjee

Niels Fricke

Timothy J Siegel

Naga P Gorti

Quintino Lorenzo Trianni

Eckhard Kunigkeit

Ehsan Fatehi

Kent Li

Hung Qui Le

Reinhard Theodor Buendgen

Jose Eduardo Moreira

Bryan J Lloyd

Albert James Van Norstrand, Jr

Bernd Nerz

Michael Joseph Genden

Otto Andreas Torreiter

Jentje Leenstra

Thomas Hermann Gnech

Kenneth Lundy Ward

Steffen Koenig

Salma Ayub

Robert Alan Philhower

Dhivya Jeganathan

Oliver Petrik

Edmund Joseph Gieske

Jessica Hui-Chun Tseng

Deepankar Bhattacharjee

Volodymyr Paprotski

Regina Illner

Jochen Roehrig

A computer system, processor, and/or method for changing the mode of operation of a computer without rebooting includes: a processor having a configuration register, the configuration register having a privilege entry (PRVS) register field for each of one or more privilege levels, each PRVS register field for each privilege level having one or more control aspect entries; and an enforce below (ENFB) register field, each ENFB register field for each privilege level having one or more control aspect entries, the PRVS register field control aspects being equal in number to and corresponding to the ENRB register field control aspects. The PRVS register fields and the ENFB register fields are used to change the processor from a secure mode to a performance mode while running software applications.

Systems and methods for dynamic control of a secure mode of operation in a processor

A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

Reducing cache transfer overhead in a system

Branch prediction in an instruction using a tag orientation predictor (TOP) is described. When a branch instruction is hotly mis-predicted by a hybrid branch predictor, the branch is tracked over a longer time period using the TOP. Once the TOP has collected enough data to confidently predict a branch prediction, the TOP is used to override a branch prediction from the hybrid predictor when the TOP branch prediction.

Hybrid and aggregrate branch prediction system with a tagged branch orientation predictor for prediction override or pass-through

Load store addressing can include a processor, which fuses two consecutive instruction determined to be prefix instructions and treats the two instructions as a single fused instruction. The prefix instruction of the fused instruction is auto-finished at dispatch time in an issue unit of the processor. A suffix instruction of the fused instruction and its fields and the prefix instruction's fields are issued from an issue queue of the issue unit, wherein an opcode of the suffix instruction is issued to a load store unit of the processor, and fields of the fused instruction are issued to the execution unit of the processor. The execution unit forms operands of the suffix instruction, at least one operand formed based on a current instruction address of the single fused instruction. The load store unit executes the suffix instruction using the operands formed by the execution unit.

Program counter (PC)-relative load and store addressing for fused instructions

In at least one embodiment, a processor includes architected and non-architected register files for buffering operands. The processor additionally includes an instruction fetch unit that fetches instructions to be executed and at least one execution unit. The at least one execution unit is configured to execute a first class of instructions that access operands in the architected register file and a second class of instructions that access operands in the non-architected register file. The processor also includes a mapper circuit that assigns physical registers to the instructions for buffering of operands. The processor additionally includes a dispatch circuit configured, based on detection of an instruction in one of the first and second classes of instructions for which correct operands do not reside in a respective one of the architected and non-architected register files, to automatically initiate transfer of operands between the architected and non-architected register files.

Processor providing intelligent management of values buffered in overlaid architected and non-architected register files

A method, computer program product, and system includes a processor obtaining data including values and generating a value conversion dictionary by applying a parse tree based compression algorithm to the data, where the value conversion dictionary includes dictionary entries that represent the values. The processor obtains a distribution of the values and estimates a likelihood for each based on the distribution. The processor generates a code word to represent each value, a size of each code word is inversely proportional to the likelihood of the word. The processor assigns a rank to each code word, the rank for each represents the likelihood of the value represented by the code word; and based on the rank associated with each code word, the processor reorders each dictionary entry in the value conversion dictionary to associate each dictionary entry with an equivalent rank, the reordered value conversion dictionary comprises an architected dictionary.

Memory preserving parse tree based compression with entropy coding

Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

Saving and restoring machine state between multiple executions of an instruction

A system, processor, and/or technique configured to: determine whether two or more load instructions are fusible for execution in a load store unit as a fused load instruction; in response to determining that two or more load instructions are fusible, transmit information to process the two or more fusible load instructions into a single entry of an issue queue; issue the information to process the two or more fusible load instructions from the single entry in the issue queue as a fused load instruction to the load store unit using a single issue port of the issue queue, wherein the fused load instruction contains the information to process the two or more fusible load instructions; execute the fused load instruction in the load store unit; and write back data obtained by executing the fused load instruction simultaneously to multiple entries in the register file.

Handling and fusing load instructions in a processor

A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.

Sort and merge instruction for a general-purpose processor

Technology for fusing an add-immediate instruction with a load-immediate instruction (or store-immediate instruction) in a microprocessor. This can result in quicker address generation while performing a load and store operation.

Fusion to enhance early address generation of load instructions in a microprocessor

In an approach to dynamic redistribution of register files, whether a redistribution of register files is necessary is determined. Responsive to determining that the redistribution of register files is necessary, one or more register file transfers that have not yet completed are flushed. One or more register file write locations are allocated for each architected register based on a register free list. Source data is read from each architected register. The source data is written to the one or more register file write locations.

Redistribution of architected states for a processor register file

Growing community of inventors

Weinstadt, Germany

Christian Zoellin