Advanced Micro Devices Corporation

Globalfoundries Inc.

Christian Zistl

Paul Raymond Besser

Eric M Apelgren

Jeremy Isaac Martin

Nicholas John Kepler

Jonathan B Smith

Srikanteswara Dakshina-Murthy

Lie Larry Zhao

Fred Cheung

Peter Huebler

Matthias Lehr

Frank Feustel

Nick Kepler

Ting Yiu Tsui

Stephen Keetai Park

Massud Aminpur

Gert Burbach

Larry Zhao

Peter H&uuml;bler

J&ouml;rg Hohage

Hartmut R&uuml;lke

Srikantewara Dakshina-Murthy

James Werking

The introduction of dielectric material of enhanced mechanical stability, such as silicon dioxide or fluorine-doped silicon dioxide, into the via level of a low-k interconnect structure provides an increased overall mechanical stability, especially during the packaging of the device. Consequently, cracking and delamination, as frequently observed in high end low-k interconnect structures, may significantly be reduced, even if organic package substrates are used.

Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging

The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.

Resist trim process to define small openings in dielectric layers

By using a non-metallic hard mask for patterning low-k dielectric materials of advanced semiconductor devices, an enhanced degree of etch fidelity is obtained. The present invention may readily be applied to via first-trench last, trench first-via last schemes.

Method of patterning a low-k dielectric using a hard mask

A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer that carries the device structure, and a window is formed in the etch stop layer. Further, a dielectric layer is formed upon the etch stop layer that has the window. Then, a first contact hole through the dielectric layer and the window down to the backside semiconductor substrate is simultaneously etched with at least one second contact hole through the dielectric layer down to the device structure. The wafer may be a silicon-on-insulator (SOI) wafer, and the etch stop layer and the dielectric layer may be formed by depositing silicon oxynitride and tetraethyl orthosilicate (TEOS), respectively. The device structure may be a CMOS transistor structure.

Simultaneous formation of device and backside contacts on wafers having a buried insulator layer

A method is provided, the method comprising forming a dielectric layer above a structure layer, forming a hard mask layer above the dielectric layer, and forming at least one trench opening and at least one upper portion of a first via opening in the dielectric layer through the hard mask layer. The method also comprises forming a low viscosity photoresist layer above the at least one trench opening and the at least one upper portion of the first via opening in the dielectric layer.

Depth of focus (DOF) for trench-first-via-last (TFVL) damascene processing with hard mask and low viscosity photoresist

A copper line that is formed in a patterned dielectric layer has a copper/silicon film formed on a surface thereof to substantially suppress an electromigration path through this surface. In an in situ process, the exposed copper surface is first cleaned by a reactive plasma ambient including nitrogen and ammonia and after a certain clean period, a gaseous compound comprising silicon, for example silane, is added to the reactive plasma ambient to form the copper/silicon film. Additionally, a capping layer may be deposited, wherein due to the copper/silicon film, any deposition technique or even spin-coating may be used.

Semiconductor device with a copper line having an increased resistance against electromigration and a method of forming the same

A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises forming a first opening in the first dielectric layer above at least a portion of the first conductive structure, the first opening having sidewalls, and densifying the sidewalls.

Locally increasing sidewall density by ion implantation

A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises densifying a portion of the first dielectric layer above at least a portion of the first conductive structure, and forming a first opening in the densified portion of the first dielectric layer.

Sidewall treatment for low dielectric constant (low K) materials by ion implantation

The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask layer above the layer of dielectric material, and forming an opening in the hard mask layer. The method further comprises forming a sidewall spacer in the opening in the hard mask layer that defines a reduced opening, forming an opening in the layer of dielectric material below the reduced opening, and forming a conductive interconnection in the opening in the dielectric layer.

Method of defining small openings in dielectric layers

A semiconductor device includes a first dielectric layer, a plurality of conductive interconnections formed in the first dielectric layer, a patterned passivation layer formed above the conductive interconnections, and a second dielectric layer formed above and in contact with the passivation layer and the first dielectric layer. A method for forming a semiconductor device includes providing a base layer, forming a first dielectric layer over the base layer, forming a plurality of conductive interconnections in the first dielectric layer, forming a patterned passivation layer above the conductive interconnections, and forming a second dielectric layer above and in contact with the passivation layer and the first dielectric layer.

Semiconductor device with partial passivation layer

The present invention is directed to a method of making a semiconductor device. In one illustrative embodiment, the method comprises forming a first layer comprised of polysilicon, forming a second layer comprised of a refractory metal above the layer of polysilicon and converting at least a portion of the second layer to a first metal silicide. The method further comprises forming an anti-reflective coating layer above the layer of refractory metal or the first metal silicide layer, and patterning the first metal silicide layer and the layer of polysilicon to define a gate stack comprised of a first metal silicide region and a layer of polysilicon, forming a plurality of source/drain regions in the substrate, forming a third layer comprised of a refractory metal above at least the gate stack and the source/drain regions, and converting at least a portion of the third layer to a second metal silicide region.

Method of forming a semiconductor device with metal silicide regions

A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first opening. The method also comprises forming a second dielectric layer above the first dielectric layer and above the first conductive structure, forming a second opening in the second dielectric layer above at least a portion of the first conductive structure, the second opening having a side surface and a bottom surface, and forming at least one barrier metal layer in the second opening on the side surface and on the bottom surface. In addition, the method comprises removing a portion of the at least one barrier metal layer from the bottom surface, and forming a second conductive structure in the second opening, the second conductive structure contacting the at least the portion of the first conductive structure. The method further comprises forming the conductive interconnect by annealing the second conductive structure and the first conductive structure.

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Dresden, Germany

Christian Zistl