Qimonda Ag

Infineon Technologies Ag

Infineon Technologies LLC

Christian Weiss

Sven Kalms

Hermann Ruckerbauer

Peter Gregorius

Simon Muff

Johannes Stecker

Ralf Schledz

The memory module comprises a circuit board with a first and a second side, wherein memory chips are arranged at least on the first side. A longitudinally extending module heat conductor is arranged on the first side. The module heat conductor comprises a contact surface configured to contact a heat transfer system.

Heat transfer system

Heat transfer system for memory modules

An electronic assembly includes electronic modules connected in a series circuit such that a particular number of input connections of one of the electronic modules is connected with the particular number of output connections of another of the electronic modules. Each electronic module is configured to pass on an information which each electronic module receives on an input side at an nth of each electronic module's input connections to an nth of each electronic module's output connections. The input connections and output connections of each electronic module are arranged in a same geometric arrangement. Each electronic module is configured to receive, irrespective of a geometric orientation of the input connections of a given electronic module in relation to a geometric orientation of the output connections of a corresponding electronic module connected with the given electronic module on the input side of the given electronic module, at the same of the given electronic module's input connections, a particular information which is transmitted by the same output connections of the corresponding electronic module.

Information transfer in electronic modules

Semiconductor memory modules and semiconductor memory systems using the same are described herein. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input lines and the rD signal output lines in a respective point-to-point fashion.

Re-driving CAwD and rD signal lines

A semiconductor memory arrangement for operation in a data memory system with at least one semiconductor memory chip for the storage of user data includes a memory controller for control of the at least one semiconductor memory chip, and at least one unidirectional signal line bus for control and address signals connected with the memory controller and branching at least once. The at least once branching bus directly connecting at least one semiconductor memory chip with the memory controller and connecting the semiconductor memory chips among each other.

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Munich, Germany

Christian Weiss