Qualcomm Incorporated

Apple Inc.

Christian Venerus

Ashok Swaminathan

Jeffrey Mark Hinrichs

Marzio Pedrali-Noy

Andrew Weil

Utku Seckin

Karthik Nagarajan

Kevin Jia-Nong Wang

Debesh Bhatta

John Abcarius

Xinxin Yu

Vikram Magoon

This disclosure is directed to a transmitter including a phase locked loop (PLL), a modulator, and a power amplifier (PA). A controller including programmable and/or hardened logic circuitry may be coupled to the PLL and the modulator. The controller may provide encoded signals based on quadrature phase shift keying (QPSK) scheme for transmission by the transmitter. In particular, the controller may provide multiple bursts of pulses indicative of data packets to the modulator. Moreover, the controller may provide instructions indicative of generating clock signals with in-phase and quadrature phases to the PLL. The PLL may generate clock signals corresponding to the in-phase and quadrature phases. As such, the transmitter may generate in-phase and quadrature output signals based on receiving each burst of pulses with either in-phase or quadrature phases.

Wireless transmitter with improved data rate

Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.

Partitioned digital-to-analog converter system

A method and apparatus for controlling a supply sensitivity of a ring oscillator stage are provided. The apparatus is configured to generate, via a voltage biasing module, a first bias signal for a PMOS biasing module based on a supply voltage and a second bias signal for a NMOS biasing module based on the supply voltage, bias, via the PMOS biasing module, triode PMOS degeneration of the inverting module based on the first bias signal, bias, via the NMOS biasing module, triode NMOS degeneration of the inverting module based on the second bias signal, receive an input via an inverting module, and output, via the inverting module, an inverted version of the received input based on the biased triode NMOS degeneration and the biased triode PMOS degeneration.

Ring oscillator architecture with controlled sensitivity to supply voltage

A droop detector includes: a plurality of input nodes, each input node configured to receive a supply voltage; an output node; a plurality of detector modules, each detector module comprises: an input terminal coupled to each input node, an output terminal coupled to the output node; and an input tracking unit configured as a voltage follower to detect a droop in the supply voltage coupled to each input node and output an output voltage that follows the supply voltage on the output terminal when the droop is detected on the supply voltage; and a comparator coupled to the output node and configured to output a control signal when the droop is detected.

Multi-input scalable rectifier droop detector

Methods, systems, and circuits for providing compensation for voltage variation are disclosed. A system includes: a voltage comparator configured to assert a control signal in response to detecting that one or more of power supply voltages droops below a threshold amount; a phase locked loop (PLL) configured to divide an output frequency for the PLL in response to the assertion of the control signal; a plurality of voltage sensors corresponding to the plurality of power supply voltages, the voltage sensors configured to output respective digital signals indicative of a voltage level of its corresponding power supply voltage; and a control circuit configured to control an oscillator frequency in the PLL during the open-loop mode responsive to the respective digital signals.

Growing community of inventors

San Diego, CA, United States of America

Christian Venerus