Infineon Technologies Ag

Siemens Aktiengesellschaft

Christian Stuempfl

Michael Bauer

Ludwig Heitzer

Jens G Pohl

Peter Strobel

Bernd Goller

Gerald Ofner

Holger Woerner

Robert-Christian Hagen

Stefan Wein

Holger Wörner

Horst Theuss

Edward Fuergut

Markus Brunnbauer

Simon Jerebic

Irmgard Escher-Poeppel

Thomas Bemmerl

Thomas Stoek

Hermann Vilsmeier

Jayaganasan Narayanasamy

Fabian Schnoy

Josef Thumbs

Bernd Roemer

Jagen Krishnan

Bernhard Zuhr

Bernhard Schaetzler

Herman Vilsmeier

Robert Christian Hagen

Syahir Abd Hamid

Mian Mian Lam

A method of forming a semiconductor device includes providing a semiconductor package comprising an electrically insulating mold compound body, a semiconductor die that is encapsulated by the mold compound body, a plurality of electrically conductive leads that each protrude out of the mold compound body, and a metal heat slug, the metal heat slug comprising a rear surface that is exposed from the mold compound body, coating outer portions of the leads that are exposed from the mold compound body with a metal coating, and after completing the coating of the outer portions of the leads, providing a planar metallic heat sink interface surface on the semiconductor device which is exposed from the mold compound body, and substantially devoid of the metal coating.

Selective plating of semiconductor package leads

A method for fabricating an electronic device includes providing a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first semiconductor die and a first solder interconnect layer applied to a main face of the first semiconductor die. The second semiconductor chip has a second semiconductor die, an insulating layer applied to a main face of the second semiconductor die, and a second solder interconnect layer applied to the insulating layer. The method further includes attaching the first semiconductor chip with the first solder interconnect layer to a first carrier and attaching the second semiconductor chip with the second solder interconnect layer to a second carrier.

Method for attaching a semiconductor die to a carrier

A method for fabricating semiconductor packages includes providing a first substrate having an aperture, providing a first semiconductor chip, connecting the first semiconductor chip to the first substrate, filling the aperture with a first insulating material and encapsulating the semiconductor chip with a second insulating material to create a first encapsulation body.

Method for fabricating a semiconductor package and semiconductor package

A method for producing an electronic component of a VQFN (very thin quad flat pack no-lead) design includes the following method steps: anchoring at least one integrated circuit element on a sacrificial substrate; contact-connecting the at least one integrated circuit element to the sacrificial substrate with formation of contact-connecting points on the sacrificial substrate; forming an encapsulation on a top side of the sacrificial substrate, the at least one anchored integrated circuit element being mounted on the top side of the sacrificial substrate; removing the sacrificial substrate, thereby uncovering a portion of the contact-connecting points on the underside of the encapsulation.

Electronic component of VQFN design and method for producing the same

The invention relates to a semiconductor device comprising through contacts through a plastic housing composition and a method for the production thereof. For this purpose, the wiring substrate has a solder deposit on which through contact elements are arranged vertically with respect to the wiring substrate and extend as far as the top side of the semiconductor device.

Semiconductor device having through contacts through a plastic housing composition and method for the production thereof

A plastic housing includes plastic external faces and the underside of the plastic housing comprises external contact areas on which external contacts are arranged. The plastic external faces are covered by a closed metal layer apart from the underside, wherein the boundary layer between plastic external faces and the closed metal layer includes exposed electrically conductive inclusions of the plastic of the housing.

Plastic housing and semiconductor component with said plastic housing

The invention pertains to a method for manufacturing an electronic component with a semiconductor element () that is contacted and fixed on a substrate surface (). The method is characterized in that the rear side of the semiconductor element and/or the substrate surface is coated with an adhesive structure consisting of a first component () that solidifies, particularly hardens or cures, and an electrically conductive second component () that does not solidify, wherein the semiconductor element is bonded to the substrate surface in a contacting fashion. The electronic component is characterized in that a structured adhesive layer arranged between the semiconductor element and the substrate surface comprises a solidifying first component () and an electrically conductive non-solidifying second component ().

Method for manufacturing an electronic component and corresponding electronic component

A semiconductor device with a thinned semiconductor chip and a method for producing the latter is disclosed. In one embodiment, the thinned semiconductor chip has a top side with contact areas and a rear side with a rear side electrode. In this case, the rear side electrode is cohesively connected to a chip pad of a circuit carrier via an electrically conductive layer. In another embodiment, the thinned semiconductor chips of this semiconductor device according to the invention have low-microdefect edge side regions with semiconductor element structures and edge sides patterned by etching technology.

Semiconductor device with a thinned semiconductor chip and method for producing the thinned semiconductor chip

An electronic circuit in a package-in-package configuration and a production method is disclosed. One embodiment provides an arrangement enveloped by an encapsulation and composed of at least one semiconductor element on an element carrier, at least one leadframe with at least one inner contact-connection, at least one inner lead running within the encapsulation, and at least one outer contact-connection led out from the encapsulation. The inner lead has an exposed inner lead section which can be contact-connected from the outer side of the package-in-package configuration.

Electronic circuit in a package-in-package configuration and production method

For the vertical electrical connection of a number of components, an electronic structure with at least two components has solderable connecting elements, which include at least one socket element and a solder ball stacked on the socket element. The socket element has a cylindrical core of an electrically conducting first material with a lateral surface, a bottom surface and a top surface. The core is surrounded with a cladding of an electrically insulating second material in such a way that the lateral surface of the core is covered by the cladding and the top surface and the bottom surface are kept free of the cladding.

Electronic structure with components connected by way of solderable connecting elements and method

An electronic circuit in a package-on-package configuration includes: a lower subassembly with a first electronic element, a first wiring carrier, a first housing with a first redistribution layer and an arrangement of solder balls disposed on the first redistribution layer and an upper subassembly with a second electronic element mounted on the lower subassembly. A method for producing the electronic circuit in a package-on-package configuration includes: adhering an upper side of the first electronic element to an underside of the first redistribution layer via a radiation-crosslinking thermoplastic adhesive.

Electronic circuit in a package-on-package configuration and method for producing the same

A structure of joining material is applied to the back surfaces of semiconductor chips in manufacturing semiconductor devices. The joining material is applied, in finely metered and structured form via a joining material jet appliance, to the back surfaces of the semiconductor chips of a divided semiconductor wafer.

Method for applying a structure of joining material to the back surfaces of semiconductor chips

A biosensor that has a smart card configuration includes a semiconductor chip including a bioactive structure and contact areas disposed on a first side of the semiconductor chip, and a rewiring substrate including contact pads, external contact areas and rewiring lines that electrically connect the contact pads to the external contact areas. The rewiring substrate covers a portion of the first side of the semiconductor chip without covering the bioactive structure, such that the rewiring substrate overlaps the contact areas of the semiconductor chip and the contact pads and the contact areas are aligned with and electrically connect to each other. In addition, a measuring apparatus is configured to receive the biosensor and conduct measurements of a fluid medium that is delivered into the measuring apparatus.

Biosensor with smart card configuration

A method for coating a structure that includes at least one semiconductor chip involves electrostatically depositing coating particles on the areas of the structure to be coated. The coating particles are first applied to a carrier and the latter is electrostatically charged with the coating particles. The structure including at least one semiconductor chip is charged electrostatically to a polarity opposite to the carrier. The carrier and/or the structure are then moved towards one another in the direction of an area of the structure to be coated until the coating particles jump to the areas of the structure to be coated and adhere there. The coating particles are liquefied by heating the area with coating particles to form a coating.

Method for coating a structure comprising semiconductor chips

An electronic component and a blank have plastic embedding compounds of a first and a second plastic layer. Semiconductor chips are embedded in the first plastic layer in such a way that their marginal sides are surrounded by a bead. The second plastic layer compensates for the unevenness of a upper boundary of the first plastic layer.

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Schwandorf, Germany

Christian Stuempfl