Fujitsu Corporation

Christian Stangier

Jawahar Jain

Subramanian K Iyer

Debashis Sahoo

Amit Narayan

Koichiro Takayama

Thomas W Sidle

In one embodiment, a method for verifying one or more particular properties of a circuit using a learning strategy to determine suitable values of particular verification parameters includes classifying each of multiple properties of a circuit according to circuit size and selecting a candidate property from the properties. The candidate property set includes one or more particular properties from each property class. The method also includes attempting to verify one or more particular properties of the circuit using the candidate property set and particular values of particular verification parameters. The method also includes determining suitable values of the particular verification parameters according the attempted verification of the particular properties of the circuit using the candidate property set and the particular values of the particular verification parameters.

Circuit verification

In one embodiment, a method for invariant checking includes executing one or more first steps of a finite state machine (FSM) corresponding to one or more binary decision diagrams (BDDs) to traverse a state space of the FSM in a first direction with respect to an initial state and an erroneous state. The method also includes, automatically and without user input, accessing a first profile corresponding to the one or more first steps of the FSM, comparing the first profile with one or more first predetermined criteria, stopping the traversal of the state space in the first direction according to the comparison between the first profile and the one or more first predetermined criteria, executing one or more second steps of the FSM to traverse the state space in a second direction with respect to the initial state and the erroneous state opposite the first direction according to a first partial result from the one or more first steps of the FSM, accessing a second profile corresponding to the one or more second steps of the FSM, comparing the second profile with one or more second predetermined criteria, stopping the traversal of the state space in the second direction according to the comparison between the second profile and the one or more second predetermined criteria, and executing one or more third steps of the FSM to traverse the state space in the first direction from the one or more first steps according to a second partial result from the one or more second steps of the FSM.

Invariant checking

A method for verifying a property associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more operations may be executed in order to generate a set of transition relations for performing a reachability analysis associated with the target circuit. An image associated with the target circuit may be partitioned into a plurality of leaves that may each represent a subset of a final image to be generated by a partitioned ordered binary decision diagram (POBDD) data structure. An analysis may be computed of one or more of the leaves using a selected one or both of conjunction and quantification operations separately.

System and method for executing image computation associated with a target circuit

In one embodiment, a system for verifying a circuit using a scheduling technique includes one or more partitioned ordered binary decision diagram (POBDD) modules that collectively generate one or more POBDDs. Each POBDD corresponds to one or more partitions of a state space of the circuit and includes a number of states and a number of nodes in the partition. The system also includes one or more cost metrics modules that collectively determine a processing cost of each of the partitions of each of the POBDDs. The system also includes one or more scheduling modules that collectively schedule processing of the partitions of the POBDDs for semiformal verification of a circuit. The schedule is based, at least in part, on the determined processing costs of the partitions of the POBDDs.

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Los Altos, CA, United States of America

Christian Stangier