Siemens Aktiengesellschaft

Infineon Technologies Ag

Christian Siemers

Joachim Bangert

Ralf Arnold

Helge Kleve

Christian Wiegand

Markus Köchy

Markus KÖCHY

A component with a logic circuit arrangement with configurable functionality, includes several data lines (), whereby at least a part of the data lines () is provided with at least one element () which may be switched between two states with different discrete resistances. The data line () is opened or closed by the element (), depending on the switched state.

Component with a logic circuit arrangement with configurable functionality

A component with a functionally-configurable circuit arrangement, has a first switch group with a voltage-dependent switching on or off of a data line and at least one second switch group generating two discrete output voltages separated by an increase in voltage and the switch states for the discrete output voltages may be stored in non-volatile memory. The switching on or off of the data line is determined by the switch state of the first switch group and a third switch group () is provided to increase the voltage increase between the first switch group () and the second switch group ().

Electrical component having configurable characteristics that are non-volatile

The invention relates to a computer containing a RAM-based primary part (Ht) with a stucturable RAM unit (). On the input side, a first crossbar switch () is located upstream of said unit and a second crossbar switch () is located downstream. Address signals () can be supplied from the first crossbar switch () to the RAN unit () or the second crossbar switch (). Output signals () can be fed back from the second crossbar switch to the first crossbar switch () and can be output. An additional control part (St) for a configurable job sequencing of the primary part (Ht) comprises a counter unit () that is synchronised with the first crossbar switch () to create counter reading signals () for the first and second crossbar switch (and). The computer is particularly suitable for integrating a global cellular automaton (GCA).

Reconfigurable global cellular automaton with RAM blocks coupled to input and output feedback crossbar switches receiving clock counter value from sequence control unit

A configurable logic circuit arrangement includes at least one multiplexer for switching logic signals. The multiplexer includes one or more data inputs and one or more control signal inputs. The at least one multiplexer () can be configured by one or more external control signal transmitter elements of the circuit arrangement during the operation of the circuit in a run-time variable manner by configuration signals that are applied to the control inputs and forwards the logical signals that are applied to the data inputs during operation of the circuit in a run-time variable manner.

Configurable logic circuit arrangement

A configurable architecture of a calculation device includes at least one individual configurable and/or reconfigurable switching device, whereby the output variables thereof form a time point tand the input variables of the switching device form a time point t. Elements are provided in order to control the output variables in a clocked manner and to store the output variables of the switching device between the time points tand t.

Reconfigurable switching device parallel calculation of any particular algorithms

The invention relates to a programmable logic device () comprising several logic blocks (A toD) with configurable characteristics, elements for linking the logic blocks to one another and a processing unit () and an input/output unit (). In addition, the linking elements have at least one configurable changeover logic block, enabling the logic blocks (A toD) to be re-configured during the operation of the logic device (). Said changeover logic block is used for the configuration of at least one of the re-configurable logic blocks (A toD) and its connection to other blocks and/or its connection to the processing unit () and/or to the input/output unit ().

Programmable logic device

The configurable hardware block is designed to read data stored in a memory according to its configuration, to process the read-out data arithmetically and/or logically and to write the data representing the result of the processing into the memory. The hardware block is capable of interacting with external hardware, thereby providing a flexible and universally applicable hardware block.

Configurable processing block capable of interacting with external hardware

A method for configuring a configurable hardware block includes implementing commands and/or command sequences of a program to be executed. The implementing step includes ascertaining a given type of subunit of a configurable hardware block, the given type of subunit being required for executing a respective command, selecting, if available, a subunit of the given type of subunit, configuring configurable connections provided around the subunit selected in the selecting step, if the subunit of the given type of subunit is found in the selecting step, and ascertaining configuration data with the step of implementing the commands and/or command sequences. The configurable hardware block is configured by using the configuration data.

Method for configuring a configurable hardware block by configuring configurable connections provided around a given type of subunit

A processor having a pipelining structure, in particular with a superscalar architecture, includes a configurable logic unit, an instruction memory, a decoder unit, an interface device, a programmable structure buffer, an integer/address instruction buffer and a multiplex-controlled s-paradigm unit linking contents of an integer register file to a functional unit with programmable structures and having a large number of data links connected by multiplexers. The s-paradigm unit has a programmable hardware structure for dynamic reconfiguration/programming while the program is running. The functional unit has a plurality of arithmetic units for arithmetic and/or logic linking of two operands on two input buses to produce a result on an output bus, a plurality of compare units having two input buses and one output bit, a plurality of multiplexers having a plurality of input buses and one or two output buses and being provided between the arithmetic units, the compare units and the register file, and a plurality of demultiplexers having one input bit and a plurality of output bits. A method is also provided for high-speed calculation with pipelining.

Growing community of inventors

Wolfsburg, Germany

Christian Siemers