Infineon Technologies Ag

Siemens Aktiengesellschaft

Qimonda Ag

Nanya Technologies Corporation

Christian Sichert

Paul Wallner

Peter Gregorius

Rainer Bartenschlager

Hermann Ruckerbauer

Dominique Savignac

Zoltan Manyoki

Yukio Fukuzo

Martin Streibl

Manfred Menke

Florian Schnabel

Jens Polney

Thomas Hein

Robert Kaiser

Norbert Wirth

Abdallah Bacha

Paul Schmölz

Ralf Schneider

Franz Freimuth

Wen-Ming Lee

Jin Suk Mun

Falk Roewer

A method for operating a memory apparatus which comprises at least two memory devices, each memory device containing at least one bank, comprising: activation of at least one word line in at least one bank on the basis of a row activation command; storage of bank information, the bank information indicating which banks per memory device contain a word line activated by the row activation command; reading/writing of memory contents from/to banks with activated word lines on the basis of the bank information.

Method of operating a memory apparatus, memory device and memory apparatus

A method of refreshing the content of a memory cell of a memory arrangement includes selectively controlling a refreshing device of the memory arrangement via an interface of the memory arrangement or by an internal control device of the memory arrangement to refresh the content of the memory arrangement.

Refreshing the content of a memory cell of a memory arrangement

An integrated circuit memory with clock-controlled memory access includes at least one data connection to input/output data, a memory cell array including memory cells to store data, a clock generator circuit to generate a clock signal, a memory circuit to store data, a control circuit to control storage of data in the memory circuit and to control output of data from the memory circuit. The memory circuit is connected to the memory cell array and to the at least one data connection. During read access to the memory cells, first and second data supplied to the memory circuit from the memory cell array are buffer-stored in the memory circuit upon first and second edges of the clock signal. The first and second data are output from the memory circuit and supplied to the at least one data connection upon third and fourth edges of the clock signal.

Memory with clock-controlled memory access and method of operating the same

An integrated circuit comprises a sampling circuit arranged at a data output of an operating section and operated by sampling edges, data packets appearing at the data output in response to a sequence of request commands, and a control section configured to produce the sampling edges, the control section comprising at least two transmission branches each comprising a copy of the operating section. Pulse trains are applied to the transmission branches which have the same waveform as the sequence of request commands and are delayed relative to one another, wherein the first pulse train is contemporaneous with the sequence of request commands. The sampling edges are produced from leading edges of the pulse trains which appear at the outputs of the transmission branches.

Integrated circuit for sampling a sequence of data packets at a data output

A bus structure comprises a plurality of driver circuits, each driver circuit comprising an input for a first signal and a terminal for an output signal wherein each driver circuit is capable of providing the output signal at the terminal upon receipt of the first signal, a parallel bus comprising a plurality of output signal lines at a receiving end, being connectable to a target component, each of the signal lines extending at least from the receiving end to the terminal of a different one of the plurality of driver circuits, such that a length of the output signal line between the receiving end and the respective driver circuits decreases in a connection order among the plurality of driver circuits, and a signal line coupled to each of the inputs of the driver circuits in the connection order.

Bus structure, memory chip and integrated circuit

A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.

Data memory system and method for transferring data into a data memory

A semiconductor memory chip in which signals are transferred as serial signal frames includes a frame decoder providing an interface between a memory core and a reception interface. The frame decoder includes a command type decoder for decoding the types of commands included in frames according to the decoded type of the commands, a memory command evaluator/generator for scheduling and preparing single commands for the core, an intermediate data buffer command evaluator/generator for scheduling and preparing control signals for an intermediate data buffer, and a system command evaluator/generator for preparing and scheduling system commands. These system commands provide timing parameters to ensure time intervals between consecutive commands within one frame or between frames and are stored in a system mode register. The operation of the frame decoder is edge-synchronized by a frame clock or a synchronization decoder clock signal which is phase-aligned to that frame clock signal.

Semiconductor memory chip

A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.

Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals

One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.

Memory device, memory controller and memory system having bidirectional clock lines

The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.

Memory system with two clock lines and a memory device

A semiconductor memory device comprises a temperature dependent voltage source for outputting a voltage at its output in dependence on a temperature measured in the semiconductor memory device. At least one memory cell is provided with at least one first transistor. The first transistor includes a first transistor body, which is connected to the output of said temperature dependent voltage source.

Semiconductor memory device

A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nsignal burst.

Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system

An integrated circuit has a first voltage generator, which is connected via a first switching element to a contact-making point for external contact making with the circuit. In addition, it has a first digital control device, via which the contact-making point is connected to a control input of the first switching element. In this case, the first control device switches the first switching element on or turns the latter off by a first digital control signal, the level of which is dependent on the potential of the contact-making point. Furthermore, the contact-making point is connected to the input of a second digital control device, which supplies a digital operating mode signal at its output, the level of which operating mode signal is dependent on the potential of the contact-making point.

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Munich, Germany

Christian Sichert