Nvidia Corporation

Lucas Digital Ltd.

Christian Rouet

Rui Manuel Bastos

Emmett Michael Kilgariff

Rui Bastos

Eric Brian Lum

Cary Phillips

Christian Amsinck

Matthew Nicholas Papakipos

John Erik Lindholm

Brian Keith Cabral

Sean Jeffrey Treichler

Dale L Kirkland

Karim Abdalla

Harold Robert Feldman Zatz

Roger L Allen

Gary M Tarolli

Craig Michael Wittenbrink

Johnny S Rhoades

Shaun Ho

Tony Louca

Jeffery B Yost

Jerome Francis Duluk, Jr

Shirish C Gadre

Mark J Kilgard

Michael J M Toksvig

Tyson J Bergland

Michael John Toksvig

John Douglas Tynefield, Jr

Daniel P Wilde

Manan Patel

Lordson L Yue

Jonathan J Dunaisky

Justin Cobb

William Craig McKnight

Barry Nolan Rodgers

Wei-Chao Chen

Pierre Souillot

Joseph Detmer

Don Bittel

John Lewis

Michael Jm Toksvig

Karim M Abdalla

Johnny B Rhoades

Updating depth related graphics data is described. Geometric primitives are processed. Pixels are generated from the primitives based on the processing, each of which has at least one corresponding depth value. Culling is performed on a first group of the pixels, based on a representation of the at least one depth related value corresponding to each. Pixels may be discarded based on the culling and upon which a second group of pixels remain. A depth related raster operations function is performed, in which data is transacted with a depth buffer. The culling function is updated in relation to the transacting. The updating is performed on the basis of a granularity, which characterizes the culling function.

Updating depth related graphics data

Techniques are disclosed for suppressing access to a depth processing unit associated with a graphics processing pipeline. The method includes receiving a graphics primitive from a first pipeline stage associated with the graphics processing pipeline. The method further includes determining that the graphics primitive is visible over one or more graphics primitives previously rendered to a frame buffer, and determining that the depth buffer is in a read-only mode. The method further includes suppressing an operation to transmit the graphics primitive to the depth processing unit. One advantage of the disclosed technique is that power consumption is reduced within the GPU by avoiding unnecessary accesses to the depth processing unit.

Low-power processing in depth read-only operating regimes

A system, method, and computer program product are provided for discarding pixel samples. The method includes the steps of completing shading operations for a pixel set including one or more pixels to generate per-sample shaded attributes according to a shader program executed by a processing pipeline. Discard information for the pixel set is evaluated and one or more per-sample shaded attributes for at least one pixel in the pixel set are discarded based on the evaluated discard information.

System, method, and computer program product for discarding pixel samples

A system, method, and computer program product are provided for anti-aliasing. During a first processing pass of a plurality of graphics primitives, z data is computed for multiple samples of each pixel in an image to generate a multi-sample z buffer. During a second processing pass of the graphics primitives, computed color values corresponding to each pixel in a color buffer that stores one color value for each pixel are accumulated.

Modulated and blended anti-aliasing

A computer-implemented method for drawing graphical objects within a graphics processing pipeline is disclosed. The method includes determining that a bypass mode for a first primitive is a no-bypass mode. The method further includes rasterizing the first primitive to generate a first set of rasterization results. The method further includes generating a first set of colors for the first set of rasterization results via a pixel shader unit. The method further includes rasterizing a second primitive to generate a second set of rasterization results. The method further includes generating a second set of colors for the second set of rasterization results without the pixel shader unit performing any processing operations on the second set of rasterization results. The method further includes transmitting the first set of pixel colors and the second set of pixel colors to a raster operations (ROP) unit for further processing.

Pixel shader bypass for low power graphics rendering

A technique for efficiently rendering content reduces each complex blend mode to a series of basic blend operations. The series of basic blend operations are executed within a recirculating pipeline until a final blended value is computed. The recirculating pipeline is positioned within a color raster operations unit of a graphics processing unit for efficient access to image buffer data.

Programmable blending in multi-threaded processing units

A system, method, and computer program product are provided for processing graphics data associated with shading. In operation, a first fragment is received. Further, the first fragment is shaded. While the first fragment is being shaded, a second fragment is received and it is determined whether at least one aspect of the second fragment conflicts with the first fragment. If it is determined that the at least one aspect of the second fragment does not conflict with the first fragment, the second fragment is shaded. If it is determined that the at least one aspect of the second fragment conflicts with the first fragment, information associated with the second fragment is stored, a third fragment is received, and the third fragment is shaded, if it is determined that at least one aspect of the third fragment does not conflict with the first fragment.

System, method, and computer program product for processing graphics data associated with shading

A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D graphics pipeline are patchable. A scheduler includes a decode table, an expansion table, and a resource table that are each patchable. The decode table translates high level instructions to an appropriate microcode sequence. The patchable expansion table expands a high level instruction to a program of microcode if the high level instruction is complex. The resource table assigns the units for executing the microcode. Addresses within each of the tables can be patched to modify existing instructions and create new instructions. That is, contents in each address in the tables that are tagged can be replaced with a patch value of a corresponding register.

Method and system for patching instructions in a shader for a 3-D graphics pipeline

A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.

Scalable shader architecture

Methods and systems for texture mapping in a computer-implemented graphics pipeline are described. A sample group is identified as including a divergent pixel. A determination is made whether an operand of an instruction executing on the divergent pixel satisfies a condition. A scheme for determining a level of detail for the texture mapping is selected depending on whether or not the condition is satisfied.

Divergent and non-divergent texture fetches

A method and apparatus of operating a shader having multiple texture or shader processing stations. That method includes feeding the output of a texture or shader processing station directly into the input of another texture or shader processing station. Further, only a subset of the processing stations has access to a shader register file.

Programmable shader having register forwarding for reduced register-file bandwidth consumption

A system and method controls the scheduling of program instructions included in a shader program for execution by a processing pipeline. One or more fence instructions may be inserted into the shader program. Each fence instruction specifies a constraint that is applied to control the scheduling of another program instruction in the shader program. Controlling the scheduling of program instructions for execution by the processing pipeline may result in a more efficient use of computing resources and improved performance.

Scheduling program instruction execution by using fence instructions

Method and apparatus for graphics processing is described. More particularly, a graphics processing subsystem capable of multi-pass graphics data processing is described. The graphics processing subsystem includes a geometry processor and a fragment processor, where output from the fragment processor is input compatible with the geometry processor. Data produced in a pass through a graphics data-processing pipeline including the fragment processor and geometry processor may be used as an input to processing during a subsequent pass. Data read from a texture map may be used to define or modify data, including vertex data, being processed in the geometry processor or the fragment processor.

Systems and methods of multi-pass data processing

A method for synchronizing divergent samples in a programmable graphics processing unit is described. In one embodiment, the method includes the steps of determining that a divergence has occurred and detecting that a first sample of a group of samples has encountered a first synch token. The method also includes the steps of determining whether each of the other samples of the group has encountered a synch token and determining whether the synch token encountered by each of the other samples of the group is the first synch token.

System and method for synchronizing divergent samples in a programmable graphics processing unit

Growing community of inventors

San Rafael, CA, United States of America

Christian Rouet