Infineon Technologies Ag

Qimonda Ag

Christian Robert Mueller

Hermann Ruckerbauer

Michael Bruennert

Ullrich Menczigar

Frank Dieter Pfirsch

Johannes Georg Laven

Franz-Josef Niedernostheide

Roman Baburske

Georg Braun

Dominique Savignac

Christian Jaeger

Alexander Philippou

Daniel Domes

Maurizio Skerlj

Ralf Arnold

Hans-Dieter Oberle

Vera Van Treek

Martin Glas

Sitt Tontosirin

Judith Specht

Stefan Buschhorn

Sitt Tontisirin

Christoph Urban

Andressa Colvero Schittler

Andre Lenze

A semiconductor module arrangement includes a housing, a first semiconductor substrate arranged inside the housing, a second semiconductor substrate arranged inside the housing, a first plurality of controllable semiconductor elements, and a second plurality of controllable semiconductor elements. During operation of the semiconductor module arrangement, each controllable semiconductor element of the first plurality of controllable semiconductor elements generates switching losses and conduction losses, the switching losses being greater than the conduction losses. Further during operation of the semiconductor module arrangement, each controllable semiconductor element of the second plurality of controllable semiconductor elements generates switching losses and conduction losses, the conduction losses being greater than the switching losses. At least a first sub-group of the first plurality of controllable semiconductor elements is arranged on the first semiconductor substrate, and at least a first sub-group of the second plurality of controllable semiconductor elements is arranged on the second semiconductor substrate.

Semiconductor module arrangement

A semiconductor arrangement includes at least one switching device, electrically coupled between a first terminal and a second terminal, at least one diode, coupled in parallel to the at least one switching device between the first terminal and the second terminal, at least one bonding pad, and at least one electrically connecting element. Each of the at least one electrically connecting element is arranged to electrically couple one of the at least one switching device to one of the at least one diode. Each electrically connecting element includes a first end, a second end, and a middle section, and for at least one of the electrically connecting element, the first end is mechanically coupled to the respective switching device, the second end is mechanically coupled to the respective diode, and the middle section is mechanically coupled to at least one of the at least one bonding pad.

Semiconductor arrangement

A semiconductor die includes a semiconductor body having first and second active portions. The first active portion includes first source regions. The second active portion includes second source regions. A gate structure extends from a first surface into the semiconductor body and has a longitudinal gate extension along a lateral first direction. A first load pad and the first source regions are electrically connected. A second load pad and the second source regions are electrically connected. A gap laterally separates the first and second load pads. A lateral longitudinal extension of the gap is parallel to the first direction or deviates therefrom by not more than 60 degree. A connection structure electrically connects the first and second load pads. The connection structure is formed in a groove extending from the first surface into the semiconductor body and/or in a wiring layer formed on the first surface.

Semiconductor die, semiconductor device and IGBT module

An embodiment of a semiconductor device includes a plurality of transistor sections separated from each other and a plurality of diode sections separated from each other. Each transistor section includes an emitter electrode and a collector electrode. Each diode section includes an anode electrode and a cathode electrode. Each transistor section is electrically coupled to a common gate pad. A ratio between an active transistor part and an active diode part of the semiconductor device is adjustable by activating a first number of the transistor sections by selectively contacting the emitter electrodes and the collector electrodes of the first number of transistor sections, and by activating a second number of the diode sections by selectively contacting the anode electrodes and the cathode electrodes of the second number of diode sections.

Semiconductor device and semiconductor arrangement comprising semiconductor devices

First and second semiconductor main-elements, each having a control electrode and a load path, the load paths connected in series between first and second supply nodes, are connected with each other via a first common node. Third and fourth semiconductor main-elements, each having a control electrode and a load path, the load paths connected in series and between a third supply node and the second supply node, are connected with each other via a second common node. A fifth semiconductor main-element has a control electrode and a load path operatively connected between the first common node and an output node. A sixth semiconductor main-element has a control electrode and a load path operatively connected between the second common node and the output node. At least two of the controllable semiconductor main-elements each include a plurality of identical controllable semiconductor subcomponents.

Semiconductor arrangement with controllable semiconductor elements

Memory controllers, memory devices and methods are provided in which test data is transmitted and signal parameters are varied. The transmitted test data is read, and based on a comparison between transmitted test data and read test data a transmitter impedance is adjusted.

Memory controller comprising adjustable transmitter impedance

An electronic device provides a stack of semiconductor chips. A redistribution layer of a first semiconductor chip is arranged at the bottom of the stack. The redistribution layer of the first semiconductor chip comprises external pads.

Electronic device having a chip stack

An interface device allows data communication between a controller and a plurality of circuit units. The interface device has a first interface for a connection to the controller, a second interface for a connection to a second circuit unit, and a third interface for a connection to a second circuit unit. An interface calibrating unit is coupled to the second and third interfaces and a non-volatile calibrating parameter memory is arranged in the interface calibrating unit or coupled to the calibrating unit. The memory is adapted to store calibrating parameters for the second and third interfaces.

Interface device, circuit module, circuit system, device for data communications and method for calculating a circuit module

A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.

Memory dies for flexible use and method for configuring memory dies

An integrated circuit includes at least one input and output circuit including: a signal terminal that provides an external contact; a protective circuit coupled to the signal terminal; an input driver and/or an output driver coupled to the signal terminal via the protective circuit; and an additional circuit including a first input coupled to the signal terminal via the protective circuit, and an output that provides a test value for operation of the input and output circuit.

Growing community of inventors

Schweinfurt, Germany

Christian Robert Mueller