Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Christian Ponte

Christelle Faucon

Olivier Giaume

Beatrice Brochier

Philippe Alves

Method of testing an integrated circuit having a flexible timing control

The present invention comprises a smart debug interface circuit for the diagnostic testing and debugging of a software application for a programmable digital processor system. The smart debug interface circuit of the present invention includes an instruction register for coupling to an instruction bus of a programmable digital processor. The instruction register is adapted to drive instructions onto the instruction bus. The instruction register couples to the instruction bus in a parallel manner. The smart debug interface circuit of the present invention includes a data register for coupling to a data bus of the programmable digital processor. The data register is adapted to read data from the data bus and couples to the data bus in a parallel manner. The instruction register and data register are each coupled to an interface port. The interface port couples the smart debug interface circuit to a host computer system. A control logic circuit is also included in the smart debug interface circuit of the present invention. The control logic circuit is coupled to the instruction register, the data register, and the interface port. The control logic circuit interfaces a debugging program on the host computer system to the programmable digital processor. Additionally, the control logic circuit interfaces the debugging program with the programmable digital processor without imposing boundary scan bus delay on the instruction bus or the data bus.

Smart debug interface circuit

The present invention comprises and interrupt controller for use with a programmable digital processor system. The interrupt controller of the present invention includes a plurality of interrupt blocks. The interrupt blocks are used for coupling to a corresponding plurality of peripheral devices. Each of the interrupt blocks are coupled to a data bus included within the interrupt controller. The interrupt controller also includes an interrupt control register. The interrupt control register is coupled to each of the interrupt blocks, and upon receiving an internal interrupt request from any of the interrupt blocks, asserts a processor interrupt request responsive to the internal interrupt request. The interrupt controller includes a processor interrupt request line adapted to couple to a programmable digital processor. The interrupt control register is coupled to the processor interrupt request line and asserts the processor interrupt request to an interrupt input of the programmable digital processor via the processor interrupt request line. The interrupt controller further includes an interrupt acknowledge line adapted to couple to the programmable digital processor. The interrupt acknowledge line is coupled to the input blocks to convey an interrupt acknowledge signal from the programmable digital processor to the interrupt blocks. The interrupt acknowledge signal is conveyed to the interrupt blocks such that each of the peripheral devices efficiently share the interrupt request input of the programmable digital processor.

Method and system for extending interrupt sources and implementing

Smart debug interface circuit for efficiently for debugging a software

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La Colle sur Loup, France

Christian Ponte