Sextant Avionique

Thales

Thomson-csf Sextant

Christian Pitot

Philippe Bieth

Gerard Colas

Alain Loge

Gérard Colas

Michel Prost

Patrice Toillon

Gerard Nemoz

Bruno Bellin

Remi Andreoletti

Marc Gatti

Olivier Le Borgne

G&eacute;rard Colas

Jacques Phelippeau

Francoise Roussel

Martinez Michel

Louis Vriz

Jean-Michel Chopin

Louis Vritz

The operational reliability of a heat pipeprovided for carrying heat dissipated by an electronic componentto a heat exchangeris tested by using the heat pipe in the reverse direction, by providing energy in the form of heat at the exchanger, and by measuring the propagation time &#x394;P of the heat from the exchanger to the electronic component. Application to heat pipe tests in onboard computers.

Method for testing a heat pipe and corresponding test device

The present invention relates to an alarm management system intended to be carried onboard an aircraft. More precisely, the invention is aimed at improving the certainty level relating to the integrity of the announcements of faults or information intended for the pilot and based on voice syntheses. For this purpose, the present invention proposes a device and a method for detecting the digital origin of an analog signal providing a validity signal (VAL) enabling the voice announcements made to the pilot to be rendered secure.

Device and method for detecting the digital origin of an analogue signal

Embodiments of the invention enable the integrity of data processed by a switch to be guaranteed better than 10undetected erroneous frames per flight hour. To do this, rules for disabling ports are included in the switch management program. These rules include a maximum absolute admissible number of erroneous frames, to a maximum relative rate of admissible erroneous frames and a minimum number of erroneous frames constituting a significance threshold. Random errors are detected at the level of each frame due to the insertion of a CRC. Deterministic or data-dependent errors able to deceive systematically the CRC check are made random by means of a frame index.

Method for improving the integrity of communication means

This switch comprises a central buffer memory () for temporarily storing the data traffic which it receives, the time for performing the routings and for carrying out the resendings of the messages that it receives. It is noteworthy in that its central buffer memory () and the accesses to this buffer memory () by its various input/output ports are managed by a sequencer () in such a way as to have an implicit measure of the timescale for storing the messages in the central buffer memory () and to minimize the number of switchings which generate consumption and electromagnetic disturbances. Advantageously, the buffer memory is embodied with the aid of several modules (A, B, C, D) operating in parallel.

Variable sized information frame switch for on-board security networks

This method enables the reconstitution of messages fragmented in packets. It comprises a process for taking a census of the packets made available to a terminal () by transmission networks (Na, Nb) and a process for the reassembling of messages from packets listed by the census-taking process. These two processes implement a table of pointers pointing at the packets made available to the terminal () by the transmission networks (Na, Nb), sorted out by membership message, said pointers being placed, for each membership message, in a stack according to the order in which the packets that they point at are made available to the terminal () and being provided with information or status fields enabling the reporting of doubles or discrepancies between the order in which the packets of a stack are made available and the natural order of the message fragments constituted by the payloads of the packets, and the fate of the packet pointed at during the reassembling process.

Method for the reconstitution of messages conveyed by one or more packet-switched transmission networks

The invention relates to the selection and sorting, by a device having access to one or more packet transmission networks, of the packets relating to it, from among the entirety of the packets made available by the networks, given that the packets respect at least two layers of protocols or even more. It consists of a method of selecting and sorting that successively implements, in respect of searches for matching addresses, two directories of addresses, the first of so-called lower levels having as elements the various possible combinations of the values taken by the addressing information contained in the service information fields of the first two levels of protocols, the second so-called higher levels having as elements the addressing information contained in the service information fields of the protocols of levels higher than two, the elements of the first and second directories being linked by compatibility links targeting those that can simultaneously be in the service information fields of a packet relevant to the device.

Apparatus for selecting and sorting packets from a packet data transmission network

This method consists in making a routing automaton carry out verifications on the integrity of the packets arriving at the packet switch, their periods of stay in the packet switch, their matching with the virtual paths that they claim to take as well as the routings proper, within the packet switch, of the datagrams that have satisfactorily undergone the verification. The routing automaton is provided with a random access memory of instructed values containing a table of virtual path local descriptors. The processing time of the automaton is divided into a repetitive sequence of time slots individually allocated to the different input ports of the packet switch.

Task management method for a packet switch routing automaton forming part of a secured packet-switching transmission network

The systematic, and possibly repeated, acquisition of several distinct quantities for exploitation by a user system by utilizing a multiplexer with staged architecture without all inputs hard-wired. Each multiplexer stage is addressed by an elementary counter chained with elementary counters for addressing lower stages. The multiplexer inputs are scanned by regularly incrementing the chain of counters. If no precaution is taken, all the multiplexer inputs are scanned without considering their possible absences. To remedy this drawback a first elementary counter addresses the first stage of adjustable counting capacity switches, the elementary counters can address intermediate stages of the switches with controllable shunting circuits, and a global counter is reconfigured, at the end of each counting cycle of the first elementary counter, by commands adjusting the first elementary counter capacity, and activating or inhibiting the shunting circuits. The stored commands are a string of instructions executed one by one.

Process and device for the sequential addressing of the inputs of a multiplexer of a data acquisition circuit

An input/output controller interacts with a central processing unit of a computer which communicates with peripheral electronic equipment. The link with the central processor unit is produced with an input serial line and at least one output serial line. It receives instructions of a first type from the central processing unit and instructions of at least a second kind which are stored in the memory external to the central processing unit. These are processed using a sequencer device which allocates time slots to the instructions according to their type. This device is especially useful in the field of avionics and flight management systems.

Offset autonomous input/output controller with time slots allocation

A method for the reception and preprocessing of digital messages, with a view to their use by a handling processor. The method associates a tag identifying each message capable of being received with a descriptor of preprocessing operations to be applied to the message. The tag of certain messages is associated with a sequence of descriptors of instructions capable of being run. The descriptor is stored in a memory at an address calculated with the aid of the tag of the associated message. Upon reception of a message, the tag of the received message is read, the address of the descriptor is determined with the aid of the tag, the descriptor is read at the address thus calculated, and the instruction sequence associated with the tag of the message is run if the descriptor is of the instruction type.

Message preprocessing operations indicated by an associated descriptor read and descriptors belonging to a category of preprocessing descriptors and a category of instruction descriptors

The disclosure relates to the acquisition of a binary analog signal at input of a digital integrated circuit after its range of voltage variation has been matched with that acceptable by the digital integrated circuit by means of a resistive divider bridge. It is usual to define the architecture of an ASIC digital integrated circuit on the basis of libraries of pre-characterized cells. The disclosed device is designed to increase the possibilities of choice open to the integrated circuit designer, in enabling him to one pre-characterized cell of a Schmitt trigger for its top switching threshold and another for its bottom switching threshold. It consists of a circuit comprising, at input, a bank of Schmitt triggers of different types, followed by a discrete-rendering logic circuit deducing the logic state of the binary input analog signal of the combination of the output states of the input Schmitt triggers.

Circuit for the acquisition of binary analog signals

Phase-locked loop oscillators that are designed to set the clock rate of electronic circuits based on combinations of logic circuits and to be integrated, at the same time as these electronic circuits, into one and the same chip. There is proposed a phase-locked loop oscillator based purely on combinations of logic circuits so as not to make use of integration techniques different from those used for the electronic circuits based on combinations of logic circuits, for which they are designed to set the clock rate.

Phase-locked loop oscillator formed entirely of logic circuits

In order to convert an analog signal of digital data transmission into a digital signal, the device embodying the invention comprises a passive analog circuit comprising a capacitor charged by the analog signal via a first resistor, the voltage at the terminals of the capacitor being applied via a second resistor, at the input of a digital circuit comprising a threshold comparator applying, to a flip-flop, a logic signal which is a function of the result of the comparison with a threshold of the voltage at the input, a means for periodically applying at the input a charge or discharge pulse so as to bring the voltage at the input back to the threshold voltage, a counting circuit for periodically determining a number representative of the analog signal, obtained from subtracting the number of discharges from the number of charges.

Low-cost integrable device for the acquisition of electric signals in

A method for detecting errors in a linear sequence of commands executed by a processor and stored in a memory at a predetermined start address, comprises the association of each word in the sequence to a bit of the start address. Before storing each sequence word into the memory, the method determines the value of an unused bit of the word so that the value of the associated bit of the start address will be equal to the result of a predetermined function applied to the bits of the word. When reading a sequence word in said memory, the method compares the result of said function applied to the bits of the word read, with the value of the associated bit of the start address, and transmits an error signal if a difference is detected.

Method and device for protecting the execution of linear sequences of

A method of selecting information usable by a local unit connected to a digital transmission system includes cyclical scanning at fixed frequency of a list of programmed conditions stored in memory, acquisition of information on the transmission channels and activation of a selection process each time that the selection information of a message has been acquired. The selection process comprises a synchronization stage which waits for the scanning process to cross the start of the list of conditions. In a comparison sequence the selection information is compared with the conditions of the list. A selection variable is produced indicating if the message being received is of interest to the local unit or not. The method may be implemented through the use of a highly integrated interface.

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Boulogne Billancourt, France

Christian Pitot