Csem Centre Suisse D'electronique Et De Microtechnique Sa

Centre Electronique Horloger S. A.

Cardiola Ltd.

Csem Centre Suisse D'electronique Et De Microtechnique Sa&#x2014;recherche Et D&#xe9;veloppement

Centre Suisse D'electronique Et De Microtechnique Sa

Societe Suisse Pour L'industrie Horlogere Management Services S.a.

Lasag S.a.

Csem-centre Suisse D'electronique Et De Microtechnique

Christian Piguet

Jean-Marc Masgonty

Jean-Felix Perotto

Larry Lapanashvili

Armin Eggli

Christian Stuerzinger

Thomas Zimmermann

Claude Arm

Pierre Marchal

Peter Masa

Jean-Claude Martin

Yan Brand

Pascal Nussbaum

Stefan Cserveny

Flavio Rampogna

Daniel Mange

Pierre-David Pfister

Eduardo Sanchez

Philippe Vuilleumier

Johannes F Gerrits

Fr&eacute;d&eacute;ric Robin

An apparatus for the cardio-synchronized stimulation of skeletal or smooth muscle, but excluding the heart muscles, in a counterpulsation mode of a patient. The apparatus comprises an active and a passive electrode for attachment to said patient, a signal processor having a configuration input for varying a time delay associated with counterpulsation mode stimulation, and a sensing system for sensing information relating to the performance of the patient's heart and for transmission of information signals to said signal processor, said signal processor producing control signal information relating to stimulation signals to be applied to said active electrode in a counterpulsation mode, a stimulation signal generator associated with said active electrode for generating stimulation signals, wireless transmission means for transmitting said control signal information from said signal processor to said stimulation signal generator whereby said stimulation signal generator applies stimulation signals to said active electrode in accordance with said signal information.

Wireless cardioresonance stimulation

An apparatus for the cardio-synchronized stimulation of skeletal or smooth muscle, but excluding the heart muscles, in a counterpulsation mode of a patient. The apparatus comprises an active and a passive electrode for attachment to said patient, a signal processor having a configuration input for varying a time delay associated with counterpulsation mode stimulation, and a sensing system for sensing information relating to the performance of the patient's heart and for transmission of information signals to said signal processor, said signal processor producing control signal information relating to stimulation signals to be applied to said active electrode in a counterpulsation mode, a stimulation signal generator Associated with said active electrode for generating stimulation signals, wireless transmission means for transmitting said control signal information from said signal processor to said stimulation signal generator whereby said stimulation signal generator applies stimulation signals to said active electrode in accordance with said signal information.

Apparatus and method for the cardio-synchronized stimulation of skeletal or smooth muscles

A system for generating addresses for a digital signal processor in which the program instructions include a code for accessing a memory associated with said processor. An address calculation circuit calculates each access address to the memory on the basis of operation codes designated by the address generation code of one of the instructions and of the content of one address register selected from said address registers. Each address generation code defines an operation code to be sent to the calculation circuit. Each of the address registers is further associated with a configuration register designated at the same time as the address register by the address generation code, and each of the configuration registers contains a set of predefined operation codes, each adapted to command a predetermined calculation operation in the calculation circuit.

System for producing addresses for a digital signal processor

A neural network having layers of neurons divided into sublayers of neurons. The values of target neurons in one layer are calculated from sublayers of source neurons in a second underlying layer. It is therefore always possible to use for this calculation the same group of weights to be multiplied by respective source neurons related thereto and situated in the underlying layer of the neural network.

Method and a system for calculating the values of the neurons of a neural network

A timekeeper equipped with a radio reception device capable of decoding Radio Data System (RDS) information and including a time base, a display for displaying time data supplied by the time base, and an adjustment control for correcting the time data. The radio reception device includes a frequency locking loop for delivering RDS type data derived from a RDS spectrum received on a high-frequency carrier; and a controller which, on the basis of the delivered RDS type data, controls the adjustment control to ensure time setting of the timekeeper. The timekeeper is portable and the radio reception device rejects the spectrum received from a frequency modulated transmitter supplying RDS data, except for the frequency band containing RDS type data.

Timekeeper with automatic time setting and time setting method for same

An adiabatic logic circuit includes bidirectional transfer members to which input variables of the circuit are applied and which are connected between a first circuit terminal connected to a clock generator whose clock signal also powers the circuit and a second circuit terminal forming its output and which assumes two logic levels as a function of the input variables. The circuit has a third terminal connected to the second terminal via its inherent capacitance and precharges the second terminal to a potential corresponding to one of the logic levels outside active phases of the clock signal.

Adiabatic logic circuit

A random access memory comprises a matrix made up of cells arranged in rows and columns and the cells are addressed row by row. Each cell of a row is connected to first and second bit lines and at least the first bit line is subdivided into a plurality of sections connected to respective inputs of an output logic gate. The memory includes read/write control circuits which apply the following logic functions to each of the first and second bit lines directly or indirectly and selectively, according to whether a required operation is a write or a read. Sel.((W.D) or {overscore (W)})) is applied to the first bit line, whilst Sel.W.D is applied to both the first and second bits lines, where &ldquo;Sel&rdquo; is a cell selection signal representative of the address, &ldquo;W&rdquo; is a write command, {overscore (W)} is a read command, &ldquo;D&rdquo; is the data to be written into the addressed cell and &ldquo;.&rdquo; indicates the AND function.

Random access memory

A D-type master-slave flip-flop includes a master unit receiving an input variable and producing two first intermediate variables, a transfer unit including at least two logic gates and a clock connection connected to one input of each of the gates, which are adapted to supply two second intermediate variables as a function of the input variable and the clock signal and are looped to the master unit, and a slave unit to form at least one output variable. Another input of a first gate of the transfer unit is connected to the master unit to receive directly the true value of one of the variables supplied by the master unit. Another input of the second gate of the transfer unit is connected to the master unit to receive therefrom the complement of the same variable. The second intermediate variables are independent of each other. The flip-flop has the advantage that it is insensitive to the slopes of the flanks of the clock signals.

D-type master-slave flip-flop

The disclosure relates to microprocessors and, more particularly, to a system for organizing and a method for the sequencing of the circuits of a microprocessor. The instruction registers are connected in chains and an inhibiting device is associated with each instruction register. Each inhibiting device has its inputs connected to the inputs of the associated register and to the clock circuit a provides and signal for the loading of the associated instruction register when it detects a predetermined combination of digits in the associated register.

Microprocessor instruction pipeline having inhibit logic at each stage

In this device, each processor (P1 to P3) is associated with at least one dressable space (R1 to R3), whereas all the processors and all the addressable spaces are in communication by way of a common communication bus (BC). Between all the processors and each addressable space is connected an intercommunicating connection node (N1 to N3), each connection node including control means (LC, D1, D2) for

System for information processing comprising plurality of processors

The invention relates to computer systems containing at least one microprocessor associated with at least one memory in which are recorded instructions of a program and/or data to be processed according to the instructions. The memory is divided up into N=2 modules, one of which has a greater capacity than the other and the access time of which increases in proportion to its capacity. The module of smallest capacity is reserved for the instructions and/or data of the programs which are the most often used and the module of larger capacity is reserved for the instructions and/or data of the programs which are the least often used. The instruction contains a code identifying the module to be used.

Hierarchical ROMs that are selectively accessed by microprocessor

In this network (R) all the cells have identical construction. Each cell is assigned a code word which defines its function which it is to provide for within the network. With a view to the configuring of the cells (Cx,y), means (1) iteratively cause the translation into each of the cells of a genome formed of a train of the successive code words. The network comprises at least one individualized functional organ (O1, O2, O3, . . . ) composed of a plurality of cells which are all characterized by a first predetermined code (&lt;MHC&gt;) forming part of said code word and formed by a number identifying the organ (O1, O2, O3, . . . ) so that these cells can collectively provide for the functionality of this organ. The cells of the latter are distributed as internal cells defined by a first predetermined value of a status code also forming part of the code word, and as membrane cells defined by a second predetermined value of the second code. The internal cells provide for the functionality of the organ and the membrane cells (MO1, MO2, MO3, . . . ) are capable of functionally isolating the internal cells from the remainder of the network and of providing for the communication of these internal cells with the remainder of the network.

Electronic system organized as a matrix network of functional cells

A memory element includes a master flip-flop (1) intended to control a slave flip-flop (2) via a transfer variable (A). The slave flip-flop (2) consists of a first gate (2a) controlled by the transfer variable (A), a clock signal (CK) and a true output variable (Q), so as to deliver a complementary output variable (NQ), and a second gate (2b) controlled by the complementary output variable (NQ) and delivering the true output variable (Q). The master flip-flop (1) includes a first gate (1a) controlled by an input variable (D), the clock signal (CK) and a third variable which is formed by the transfer variable (A). The master flip-flop (1) also includes a second gate (1b) controlled by the output (B) from the first gate (1a) of the master flip-flop (1) and delivering the transfer variable (A). The first gate (2a) of slave flip-flop (2) includes, in order to accomplish the transfer of the input signal, only seven transistors at most.

Growing community of inventors

Neuchatel, Switzerland

Christian Piguet