Infineon Technologies Ag

Osram Opto Semiconductors Gmbh

Osram Opto Semiconductor Gmbh

Christian Neugirg

Peter Scherl

Peter Brick

Julius Muschaweck

Stephan Kaiser

Gerhard Kuhn

Ales Markytan

Ivan Nikitin

Andreas Grassmann

Wolfram Hable

Ottmar Geitner

Adrian Lis

Joachim Frank

Frank Winter

Uli Hiller

Inpil Yoo

Michael Niendorf

Oliver Markus Kreiter

Alexander Schwarz

Ludwig Busch

Ewald Guenther

A semiconductor package includes: a first substrate having a first metallized side; a semiconductor die attached to the first metallized side of the first substrate at a first side of the die, a second side of the die opposite the first side being covered by a passivation, the passivation having a first opening that exposes at least part of a first pad at the second side of the die; a thermally and electrically conductive spacer attached to the part of the first pad that is exposed by the first opening in the passivation, the spacer at least partly overhanging the passivation along at least one side face of the semiconductor die; a second substrate having a first metallized side attached to the spacer at an opposite side of the spacer as the semiconductor die; and an encapsulant encapsulating the semiconductor die and the spacer. Additional spacer embodiments are described.

Semiconductor package having a thermally and electrically conductive spacer

A semiconductor package includes a first power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the first power electronics carrier, and a first pair of metal pads that are immediately laterally adjacent one another and are low-voltage difference nodes of the semiconductor package, a second pair of metal pads that are immediately laterally adjacent one another and are high-voltage difference nodes of the semiconductor package, and an encapsulant body of electrically insulating material that encapsulates the power semiconductor die and the first and second pairs of metal pads, wherein the first pair of the metal pads are laterally isolated from one another by a first minimum separation distance, and wherein the second pair of the metal pads are laterally isolated from one another by a second minimum separation distance that is greater than the first minimum separation distance.

Semiconductor package with power electronics carrier having trench spacing adapted for delamination

A power semiconductor module includes a leadframe having a first die pad, a second die pad separated from the first die pad, a first power lead formed as an extension of the first die pad, a second power lead separated from the first and second die pads, and a first connection region formed as an extension of the second power lead alongside the second die pad. A first plurality of power semiconductor dies is attached to the first die pad and electrically coupled in parallel. A second plurality of power semiconductor dies is attached to the second die pad and electrically coupled in parallel. A first electrical connection extends between the first plurality of power semiconductor dies and the second die pad in a first direction. A second electrical connection extends between the second plurality of power semiconductor dies and the first connection region in the first direction.

Power semiconductor module

A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.

Semiconductor chip package comprising substrate, semiconductor chip, and leadframe and a method for fabricating the same

A method of manufacturing a power module comprising two substrates is provided, wherein the method comprises disposing a compensation layer of a first thickness above a first substrate; disposing a second substrate above the compensation layer; and reducing the thickness of the compensation layer from the first thickness to a second thickness after the second substrate is disposed on the compensation layer.

Power module comprising two substrates and method of manufacturing the same

A semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate. An important aspect in development of the semiconductor chip package is improvement of connections between different components within the package.

Semiconductor chip package comprising a leadframe connected to a substrate and a semiconductor chip, and a method for fabricating the same

An electronic module is provided, which comprises a first carrier; an electronic chip comprising at least one electronic component and arranged on the first carrier; a spacing element comprising a surface arranged on the electronic chip and being in thermal conductive connection with the at least one electronic component; a second carrier arranged on the spacing element; and a mold compound enclosing the electronic chip and the spacing element at least partially; wherein the spacing element comprises a material having a CTE value being matched with at least one other CTE.

Electronic module and method of manufacturing the same

A surface light guide includes a radiation exit area running along a main extension plane of the surface light guide and includes a light guiding region, which has scattering locations and a coating arranged on a first main area of the light guiding region, wherein radiation coupled in along the main extension plane impinging on the first main area after scattering at the scattering locations has an excessively increased radiation component and the coating reduces in a targeted manner an exit of the excessively increased radiation component from the radiation exit area.

Surface light guide and planar emitter

The invention relates to a surface light source with a lighting surface that includes at least one semiconductor body that emits electromagnetic radiation from its front side during operation. Decoupling structures are suitable for producing a local variation of the light density on the lighting surface, so that the light density is increased in at least one illumination area with respect to a background area.

Surface light source

A surface light guide has a radiation exit area extending along a main extension plane of the surface light guide and is provided for laterally coupling radiation. The surface light guide includes scattering locations for scattering the coupled radiation. The surface light guide includes a first boundary surface and a second boundary surface which delimit the light conductance of the coupled-in radiation in the vertical direction. A first layer and a second layer are formed on each other in the vertical direction between the first boundary surface and the second boundary surface. Further disclosed are a planar emitter including at least one surface light guide.

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Wuppertal, Germany

Christian Neugirg