Broadcom Corporation

Marvell Asia Pte., Ltd.

Christian Lutkemeyer

Oscar Ernesto Agazzi

Pieter Vorenkamp

Kevin Tunghai Chan

Gottfried Ungerboeck

Keshab K Parhi

Myles H Wakayama

Scott A Smith

An Integrated Circuit (IC) includes electronic circuitry, multiple sensors, and an Adaptive Voltage Scaling (AVS) circuit. The electronic circuitry is configured to be powered by one or more supply voltages. The multiple sensors are configured to measure values affected by the one or more supply voltages, and to produce multiple sensor outputs. The AVS circuit is configured to adaptively set the one or more supply voltages by applying to the sensor outputs an AVS model having one or more user-defined parameters, to generate performance data based on the sensor outputs, to export the performance data from the IC, to receive the one or more user-defined parameters into the IC in response to the performance data, and to configure the AVS model to operate in accordance with the received user-defined parameters.

User-configurable adaptive voltage scaling (AVS)

Herein described is a method and system of implementing integrated circuit logic modules that provide maximum efficiency and minimum energy dissipation. In a representative embodiment, a method of implementing one or more digital signal processing functions comprises determining one or more parameters associated with generating an optimal logic module. The one or more parameters may comprise the circuit area of the logic module and the processing time through a critical path of the logic module. In a representative embodiment, the system comprises a logic module that utilizes four full adders arranged in a tree configuration. In a representative embodiment, the logic module comprises a carry-save accumulator that provides maximum efficiency and minimal energy dissipation.

Implementation of digital signal processing functions using maximal efficiency and minimal energy dissipation

Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation precoding is performed on signals transmitted over an optical channel. In one implementation precoding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.

System and method for high speed communications using digital signal processing

Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation preceding is performed on signals transmitted over an optical channel. In one implementation preceding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.

Disclosed herein is a method and system to reduce the area and power dissipation in digital filters or multipliers Compared to radix-4 Booth coding the proposed method reduces the number of partial products by one, if the input signal has certain limits on its range. One exemplary application is echo cancellation in a full duplex pulse amplitude modulation system with 10 levels (PAM-10). Echo cancellation may be achieved by calculating a digital replica of the echo from the transmission channel. The replica signal may be calculated in a finite impulse response (FIR) filter, which multiplies the transmitted signal with estimates of the echo coefficients of the transmission channel The replica signal may be subtracted from the received signal to create an echo-free receive signal. The disclosed method may reduce the number of partial products between the PAM-10 transmit signal and each echo coefficient from three, when radix-4 Booth coding is used, to two. This in turn may reduce the number of adders in each tap multiplier of the FIR filter from two to one, resulting in lower area, lower power dissipation, and potentially higher switching speeds.

Hardware efficient implementation of finite impulse response filters with limited range input signals

Disclosed herein is a method and system to reduce the area and power dissipation in digital filters or multipliers. Compared to radix-4 Booth coding the proposed method reduces the number of partial products by one, if the input signal has certain limits on its range. One exemplary application is echo cancellation in a full duplex pulse amplitude modulation system with 10 levels (PAM-10). Echo cancellation may be achieved by calculating a digital replica of the echo from the transmission channel. The replica signal may be calculated in a finite impulse response (FIR) filter, which multiplies the transmitted signal with estimates of the echo coefficients of the transmission channel. The replica signal may be subtracted from the received signal to create an echo-free receive signal. The disclosed method may reduce the number of partial products between the PAM-10 transmit signal and each echo coefficient from three, when radix-4 Booth coding is used, to two. This in turn may reduce the number of adders in each tap multiplier of the FIR filter from two to one, resulting in lower area, lower power dissipation, and potentially higher switching speeds.

A system and method for reducing power consumption in digital circuitry by reducing the amount of unnecessary switching in such circuitry. An aspect of the present invention provides a switching-reduction circuit that outputs a signal to a subsequent digital circuit. The value of the signal may depend on the relevance of the signal value to a next output of the subsequent digital circuit. A method according to various aspects of the present invention includes receiving a next input signal. The method further includes determining whether the next input signal may be relevant to a next output of a subsequent digital circuit. The method further includes providing the next input signal to the subsequent digital circuit when the next input signal may be relevant to the next output of the subsequent digital circuit, and providing a previous signal to the subsequent digital circuit when the next input signal will not be relevant to the next output of the subsequent digital circuit.

Switching activity reduced coding for low-power digital signal processing circuitry

Disclosed herein is a method and system to reduce the area and power dissipation in digital filters or multipliers. Compared to radix-4 Booth coding the proposed method reduces the number of partial products by one, if the input signal has certain limits on its range. One exemplary application is echo cancellation in a fill duplex pulse amplitude modulation system with 10 levels (PAM-10). Echo cancellation may be achieved by calculating a digital replica of the echo from the transmission channel. The replica signal may be calculated in a finite impulse response (FIR) filter, which multiplies the transmitted signal with estimates of the echo coefficients of the transmission channel. The replica signal may be subtracted from the received signal to create an echo-free receive signal. The disclosed method may reduce the number of partial products between the PAM-10 transmit signal and each echo coefficient from three, when radix-4 Booth coding is used, to two. This in turn may reduce the number of adders in each tap multiplier of the FIR filter from two to one, resulting in lower area, lower power dissipation, and potentially higher switching speeds.

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Irvine, CA, United States of America

Christian Lutkemeyer