Intel Corporation

Infineon Technologies Austria Ag

Infineon Technologies Ag

Christian Lindholm

Matteo Camponeschi

Martin Clara

Giacomo Cascio

Kameran Azadet

Albert Molina

Daniel Gruber

Hundo Shin

Michael Fulde

Jose Luis Ceballos

Patrizia Greco

Harneet Khurana

Elmar Bach

Karl Norling

Edwin Thaller

Kannan Rajamani

Simone Fabbro

Henrik Hassander

A multi-step analog-to-digital converter (ADC). The ADC includes a sampling circuitry, a comparator, a trimming circuitry, and a DC offset actuator. The sampling circuitry is configured to sample an input analog signal. The comparator is for comparing the input analog signal sample or a residual component of the input analog signal sample to a reference value in each step. The trimming circuitry is configured to receive at least one low-order bit (e.g., a least significant bit and/or a second-least significant bit) of digital binary bits of each input analog signal sample and average the low order bit over a plurality of input analog signal samples and generate a control signal for correcting an input DC offset of the comparator based on an average value of the low-order bits. The DC offset actuator is configured to correct the input DC offset of the comparator based on the control signal.

Method and system for digital background offset correction of a comparator in an analog-to-digital converter

A successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of differential capacitive digital-to-analog converters (C-DACs), comparators, and an SAR controller. Each differential C-DAC comprises a pair of C-DACs for positive and negative polarities and each C-DAC comprises a capacitor array. A capacitor for each bit position may include a pair of equal-sized capacitors. Each outer comparator is coupled to one of the differential C-DACs and the middle comparator is coupled to a differential output node pair of C-DACs from two differential C-DACs. The SAR controller generates a control signal for the differential C-DACs for each conversion step based on outputs of the comparators. The outputs of the comparators are provided to the differential C-DACs as the control signal without encoding. Single-bit/cycle shorting switches for shorting top plates of capacitors of the C-DACs of same polarity may be closed during a single-bit/cycle conversion.

Successive approximation register analog-to-digital converter

An apparatus for analog-to-digital conversion is provided. The apparatus includes a first analog-to-digital converter (ADC) configured to receive an input signal and convert the input signal to a sequence of M-bit digital values. The apparatus further includes a second ADC including a plurality of time-interleaved sub-ADCs each being configured to receive the input signal and at least one M-bit digital value of the sequence of M-bit digital values. Further, each of the plurality of time-interleaved sub-ADCs is configured to convert the input signal to a respective sequence of B-bit digital values using the at least one M-bit digital value of the sequence of M-bit digital values. M and B are integers with M<B.

Apparatus for analog-to-digital conversion, systems for analog-to-digital conversion and method for analog-to-digital conversion

A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node.

Reference buffer circuit, analog-to-digital converter system, receiver, base station and mobile device

An analog-to-digital converter comprising a plurality of sampling cells. At least one of the plurality of sampling cells comprises a capacitive element coupled to a cell output of the at least one of the plurality of sampling cells, wherein a cell output signal is provided at the cell output. The at least one of the plurality of sampling cells further comprises a first cell input for receiving an input signal to be digitized, and a second cell input for receiving a calibration signal. Additionally, the at least one of the plurality of sampling cells comprises a first switch circuit capable of selectively coupling the first cell input to the capacitive element based on a clock signal, and a second switch circuit capable of selectively coupling the second cell input to the capacitive element, wherein a size of the second switch circuit is smaller than a size of the first switch circuit.

Analog-to-digital converter and method for calibrating the same, method for calibrating a pipelined analog-to-digital converter, receiver, base station and mobile device

An input buffer circuit for an analog-to-digital converter is provided. The input buffer circuit includes a buffer amplifier. The buffer amplifier includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair for the analog-to-digital converter. The buffer amplifier further includes a first output node and a second output node each configured to output a respective one of a first buffered signal and a second buffered signal. In addition, the input buffer circuit includes feedback circuitry. The feedback circuitry is configured to generate, based on the first buffered signal and the second buffered signal, a first feedback signal and a second feedback signal for mitigating a respective unwanted signal component at the first input node and the second input node related to a limited reverse isolation of the amplifier buffer. The feedback circuitry is further configured to supply the first feedback signal to the first input node and the second feedback signal to the second input node.

Input buffer circuit, analog-to-digital converter system, receiver, base station, mobile device and method for operating an input buffer circuit

A method and system for controlling an analog-to-digital converter (ADC) in an observation path in a transceiver. The transceiver includes a transmit path, a receive path, and an observation path. The observation path includes an analog buffer and an observation ADC. A controller generates a control signal to control sampling events at the observation ADC to activate the observation ADC at combined uniform and non-uniform sampling instants. The controller may also generate a second control signal indicating whether digital data obtained by the observation ADC is valid or not. The digital data generated by the observation ADC at non-uniform sampling instants is indicated as invalid and digital data generated by the observation ADC at uniform sampling instants is indicated as valid. The digital data indicated as invalid may be discarded and the digital data indicated as valid is used for calibration of the transmit path or the receive path.

Transceiver and method and system for controlling an analog-to-digital converter in an observation path in the transceiver

The present disclosure relates to a bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station, and a mobile station. The bootstrapped switch circuit comprises an output for an output signal, a first input, a switching element configured to couple the output with a signal from the first input, a bootstrapper capacitor configured to drive the switching element, and a second input coupled to the bootstrapper capacitor.

Bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station and a mobile device

An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.

Analog-to-digital converter system, transceiver, base station and mobile device

A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.

Analog-to-digital conversion

An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.

Analog-to-digital converter

A time-interleaved Analog-to-Digital Converter, ADC, system is provided. The time-inter-leaved ADC system includes time-interleaved first and second ADC circuits and a switching circuit. The switching circuit is configured to selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground, and to selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground. Further, the time-interleaved ADC system includes an output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal.

Time-interleaved analog-to-digital converter system

A n-bit Successive Approximation Register Analog-to-Digital Converter, SAR ADC, is provided. The SAR ADC comprises a respective plurality of sampling cells for each bit of the n-bit of the SAR ADC. Each sampling cell comprises a capacitive element coupled to a cell output of the sampling cell in order to provide a cell output signal. Further, each sampling cell comprises a first cell input for receiving a first signal, and a first switch circuit capable of selectively coupling the first cell input to the capacitive element. Each cell additionally comprises a second cell input for receiving a second signal, and a third cell input for receiving a third signal. The third signal exhibits opposite polarity compared to the second signal. Each sampling cell comprises a second switch circuit capable of selectively coupling one of the second cell input and the third cell input to the capacitive element. The SAR ADC further comprises at least one comparator circuit coupled to the sampling cells. The at least one comparator circuit is configured to output a comparison signal based on the cell output signals of the sampling cells. Additionally, the SAR ADC comprises a calibration circuit configured to supply at least one respective control signal to the respective second switch circuit of the sampling cells for controlling the second switch circuits.

n-Bit successive approximation register analog-to-digital converter and method for calibrating the same, receiver, base station and mobile device

The present disclosure relates to a time-interleaved ADC circuit. The time-interleaved ADC circuit comprises an input for an analog input signal, a first ADC bank comprising a first plurality of parallel time-multiplexed ADCs, wherein the first plurality of parallel time-multiplexed ADCs is configured to subsequently generate a first plurality of samples of the analog input signal during a first time interval, a first buffer amplifier coupled between the input and the first ADC bank. The time-interleaved ADC circuit further comprises a second ADC bank comprising a second plurality of parallel time-multiplexed ADCs, wherein the second plurality of parallel time-multiplexed ADCs is configured to subsequently generate a second plurality of samples of the analog input signal during a second time interval, wherein the first and the second time intervals are subsequent time intervals, a second buffer amplifier coupled between the input and the second ADC bank. The first ADC bank has associated therewith a first dummy sampler, wherein the ADC circuit is configured to activate the first dummy sampler before the start of the first time interval. The second ADC bank has associated therewith a second dummy sampler, wherein the ADC circuit is configured to activate the second dummy sampler before the start of the second time interval.

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Villach, Austria

Christian Lindholm