International Business Machines Corporation

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Ultratech, Inc.

Globalfoudries Inc.

Christian Lavoie

Cyril Cabral, Jr

Ahmet Serkan Ozcan

Zhen Zhang

Guy M Cohen

Paul Michael Solomon

Bin Yang

Kevin K Chan

Emre Alptekin

Praneet Adusumilli

Yun Yu Wang

Kathryn Turner Schonenberg

Conal Eugene Murray

Hemanth Jagannathan

Kenneth Parker Rodbell

Clement Hsingjen Wann

Zhijiong Luo

Marwan H Khater

Stephen Mark Rossnagel

Kangguo Cheng

Bruce Bennett Doris

Ali Khakifirooz

Markus Brink

Anna Wanda Topol

Josephine B Chang

Vijay Narayanan

Michael A Guillorn

Alfred Grill

Kirk David Peterson

Kern Rim

Chengwen Pei

Zhengwen O Li

Renee Tong Mo

Yun-Yu Wang

Chih-Chao Yang

Huilong Zhu

John J Ellis-Monaghan

Dechao Guo

Shom Ponoth

Keith Kwong Hon Wong

Jack Oon Chu

John Michael Cotte

Nicholas Anthony Lanzillo

Pranita Kerber

Thomas M Shaw

Terry Allen Spooner

Phaedon Avouris

James Spiros Nakos

Hon-Sum Philip Wong

Devendra K Sadana

Brent A Anderson

Takashi Ando

Effendi Leobandung

Tak H Ning

Balasubramanian Pranatharthiharan

Ying Di Zhang

Katherine Lynn Saenger

Michael Patrick Chudzik

Eugene John O'Sullivan

Paul Alfred Lauro

David William Abraham

Wilfried Haensch

Da-Yuan Shih

Brian Joseph Greene

Pranita Kulkarni

Jin Cai

Steven John Koester

Rajarao Jammy

Stephen L Buchwalter

Viorel C Ontalus

Kwong Hon Wong

Sung Kwon Kang

Chun-Yung Sung

Lawrence Alfred Clevenger

Ghavam G Shahidi

Nicolas J Loubet

Oleg Gluschenkov

Ramachandra Divakaruni

Paul Raymond Besser

Davood Shahrjerdi

Jeehwan Kim

Takeshi Nogami

Benjamin David Briggs

Hariklia Deligianni

Jeng-Bang Yau

Joel Pereira De Souza

Martin Michael Frank

Shreesh Narasimha

Teodor Krassimirov Todorov

Kuen-Ting Shiu

Kisik Choi

Omer H Dokumaci

Unoh Kwon

Oki Gunawan

Yu Zhu

Qiqing Christine Ouyang

Robert L Wisnieff

Nathan P Marchack

Roger Allan Quon

Harold John Hovel

An interconnect structure including conducting layers of topological semi-metals and/or topological insulators. To increase charge carrier density in the conducting layers, a charge carrier doping layer present on at least one surface of the one or more conductive layers of topological semi-metals. The charge carrying doping layers have a charge carrier density greater than the topological semi-metals and/or topological insulators of the one or more conductive layers.

Multi-layer topological interconnect with proximal doping layer

Techniques facilitating formation of amorphous superconducting alloys for superconducting circuits are provided. A device can comprise one or more superconducting components that comprise an amorphous superconducting alloy comprising two or more elements. At least one element of the two or more elements is a superconducting element.

Amorphous superconducting alloys for superconducting circuits

A method of increasing grain size of polycrystalline superconducting materials for superconducting circuits, includes forming an initial superconducting epitaxial layer lattice matched to a substrate formed of a substrate material, the initial superconducting epitaxial layer formed of a compound including the substrate material and a first metal; and forming a second layer of the first metal on the initial superconducting epitaxial layer and heating the layers to increase a thickness of the initial superconducting epitaxial layer formed of the compound.

Increasing grain size of polycrystalline superconducting materials for superconducting circuits

A semiconductor device includes a substrate including designated source or drain (source/drain) regions. An active source/drain is in the designated source/drain regions, and a source/drain cap liner is on an upper surface of the active source/drain. The semiconductor device further includes trench silicide regions completely filed with a silicide material.

Liner-free resistance contacts and silicide with silicide stop layer

A superconducting circuit includes a Josephson junction device including a lower superconducting material layer formed on a substrate and a junction layer formed on the lower superconducting material layer. The superconducting circuit also includes an upper superconducting material layer formed over the junction layer. At least the lower superconducting material layer comprises grains having a size that is larger than a size of the Josephson junction.

Grain size control of superconducting materials in thin films for Josephson junctions

A method of fabricating a superconductor device includes providing a first metal layer on top of the substrate. An oxidation of a top surface of the first metal layer is rejected. A second metal layer is deposited on top of the second metal layer. A superconducting alloy of the first metal layer and the second metal layer is created between the first metal layer and the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.

Superconducting structure and device surface termination with alloy

A method of measuring contact resistance at an interface for superconducting circuits is provided. The method includes using a chain structure of superconductors to measure a contact resistance at a contact between contacting superconductor. The method further includes eliminating ohmic resistance from wire lengths in the chain structure by operating below the lowest superconducting transition temperature of all the superconductors in the chain structure. The measurement is dominated by contact resistances of the contacts between contacting superconductors in the chain.

Methods and structure to probe the metal-metal interface for superconducting circuits

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.

Low resistance source-drain contacts using high temperature silicides

The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.

Interconnect with self-forming wrap-all-around barrier layer

Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.

Techniques to improve reliability in Cu interconnects using Cu intermetallics

A semiconductor device includes epitaxially grown source/drain (S/D) regions each having a cross-sectional quadrilateral shape formed on a semiconductor fin on opposite sides of a transversely disposed gate structure. The S/D regions include top (111) facets on top halves of the cross-sectional quadrilateral shape. The device further includes a silicide formed on the top (111) facets.

Thermally stable salicide formation for salicide first contacts

A method for forming a salicide includes forming, on at least one semiconductor fin, at least one source/drain (S/D) region including a (111) facet and having a cross-sectional quadrilateral shape, forming a conductive material on the (111) facet, annealing the conductive material to form a silicide on the (111) facet, and forming at least one contact to the silicide.

Forming thermally stable salicide for salicide first contacts

Technical solutions are described for configuring a synaptic array. An example computer implemented method includes selecting a first electronic circuit and a second electronic circuit from the synaptic array for executing a task. The method further includes connecting the first electronic circuit to the second electronic circuit to facilitate passage of electric current by forming a metallic protrusion to connect a first connector of the first electronic circuit and a second connector of the second electronic circuit.

Metallic synapses for neuromorphic and evolvable hardware

Growing community of inventors

Ossining, NY, United States of America

Christian Lavoie