Cirrus Logic Inc.

Conexant Systems, Inc.

Cirrus Logic International Semiconductor Limited

Christian Larsen

Lorenzo Crespi

Eric Jerome King

Lingli Zhang

Jeffrey Allen May

John L Melanson

John Christopher Tucker

Gautham Devendra Kamath

Graeme G Mackay

Ullas Pazhayaveetil

Yongjie Cheng

Mouna Elkhatib

Marc Laurent Tarabbia

Ketan B Patel

Anu Chakravarty

Gomathi Komanduru

Ravi Kishore Kummaraguntla

Aaron J Brennan

Ajit Sharma

Brian W Friend

Xin Fan

Kathryn Rose Holland

Shanjen Pan

Lakshmi P Murukutla

Anthony Stephen Doy

Johann Guy Gaboriau

Alexander Barr

Jason William Lawrence

Lei Zhu

Emmanuel A Marchais

Eric Kimball

Vamsikrishna Parupalli

Paul Wilson

Wesley Ladd Mokry

James Walter Wihardja

Dan Shen

Mark R Tennyson

Scott Warrick

Hasnain Akram

James Bunde Villadsen Skov

Justin Dougherty

Jonathan Chien

Wei Xu

Vivek Jindal

Terence C Bowness

Neel Pramanik

Mary Xiao-Hua Lu

Mary X Lu

James Bunde Viliadsen Skov

Ying Ying

Adrian Colli-Menchi

Mujo Kozak

Jingjing Yu

Eric Eklund

Bo-Ren Wang

David Kostusiak

Katy Holland

Michael R Kobe

Huan Wang

A method for enforcing design rules in a circuit layout may include providing a circuit schematic for an integrated circuit to a circuit simulator, wherein the circuit layout is derived from a circuit schematic, using the circuit simulator to simulate the circuit schematic and generate simulated electrical parameters for the integrated circuit, and using the simulated electrical parameters to enforce physical design rules when generating the circuit layout based on the simulated electrical parameters.

Enforcing simulation-based physical design rules to optimize circuit layout

An apparatus may include a sense resistor comprising a plurality of parallel-coupled resistor elements, a plurality of positive voltage sense points, and a plurality of negative voltage sense points. A first passive combination network may be configured to combine the plurality of positive voltage sense points into a single positive sense terminal and a second passive combination network may be configured to combine the plurality of negative voltage sense points into a single negative sense terminal. The first passive combination network and the second passive combination network may be arranged such that a sense voltage is measurable between the single positive sense terminal and the single negative sense terminal and a dependence of the sense voltage on a variation in current density in the parallel-coupled resistor elements is minimized.

Sense resistor and method for forming same

A system may include a power converter having a maximum allowable input power drawn from a power source, an energy storage element coupled to an output of the power converter at a top plate of the energy storage element, wherein the energy storage element is configured to store excess energy, and control circuitry configured to, when an input power of the power converter exceeds the maximum allowable input power, cause excess energy stored in the energy storage element to be consumed by circuitry coupled to the output of the power converter, and in order to maintain positive voltage headroom for the circuitry coupled to the output of the power converter, selectively couple a bottom plate of the energy storage element to the power source such that excess energy stored by the circuitry coupled to the output of the power converter is consumed from the energy storage device when the input power of the power converter exceeds the maximum allowable input power.

Efficient use of energy in a switching power converter

A power converter may include an input for receiving an input signal and output for generating an intermediate signal that is a power converted signal from the input signal wherein the intermediate signal is determined based on various parameters of a signal path that utilizes the intermediate signal, wherein the various parameters comprise one or more of the following: a peak output signal of the signal path, energy requested over a period of time by the signal path, available energy from an energy source to the power converter, stored energy at an output of the power converter, and stored energy of a battery for providing electrical energy at the input.

Signal tracking-based supply voltage generation with over-boosted voltage

A system may include a front end differential amplifier having two input terminals, two input resistors, each of the two input resistors coupled to a respective one of the two input terminals, and an input common mode biasing circuit for an output stage of the front end differential amplifier, the input common mode biasing circuit comprising two current sources configured to generate currents for biasing the output stage of the front end differential amplifier.

Current sensing circuitry

A method for operating a charge pump having a variable switching frequency may include comparing a target minimum output voltage with an output voltage generated at an output of the charge pump and controlling switching of switches of the charge pump based on the comparison such that the variable switching frequency varies as an output current driven by the charge pump varies.

Variable-frequency charge pump using output voltage threshold control

A system may include a power converter having a maximum allowable input power drawn from a power source, an energy storage element coupled to an output of the power converter at a top plate of the energy storage element, wherein the energy storage element is configured to store excess energy, and control circuity configured to, when an input power of the power converter exceeds the maximum allowable input power, cause excess energy stored in the energy storage element to be consumed by circuitry coupled to the output of the power converter, and in order to maintain positive voltage headroom for the circuitry coupled to the output of the power converter, selectively couple a bottom plate of the energy storage element to the power source such that excess energy stored by the circuitry coupled to the output of the power converter is consumed from the energy storage device when the input power of the power converter exceeds the maximum allowable input power.

A system may include an integrated circuit comprising an on-chip power supply and an internal power rail, a gate-controlled supply switch configured to be coupled between the on-chip power supply and an external power supply such that the internal power rail is regulated by the on-chip power supply when the gate-controlled supply switch is open and the internal power rail is regulated by the external power supply when the gate-controlled supply switch is closed, and a control circuit configured to monitor conditions associated with the on-chip power supply when the gate-controlled supply switch is transitioning between switch states and based on the conditions, control a rate of charging or discharging of a capacitance coupled to a gate of the gate-controlled supply switch.

Managing on-chip power rail between internal power supply and external power supply

A high CMRR current monitoring circuit includes a first stage that receives a current sense signal, a voltage across a current sense resistor in series with an output of a class-D amplifier. First stage is powered by at least one floating supply and/or reference that tracks the amplifier output. First stage applies gain to the current sense signal to generate an intermediate signal. A second stage receives the intermediate signal and is powered by a ground-referenced supply and provides an amplified representation of the current sense signal. The floating supply is supplied by a capacitive-coupled power source driven by the ground-referenced supply. The second stage output may be a voltage relative to ground or a digital signal. The intermediate signal may be a current, digital signal, or amplified version of the current sense signal voltage. The first stage may be a transconductance amplifier and the second stage a transimpedance amplifier.

High common mode rejection ratio (CMRR) current monitoring circuit using floating supplies

Transistors may be manufactured with a shared drain to reduce die area consumed by circuitry. In one example, two transistors can be manufactured that include two body regions that abut a shared drain region. The two transistors can be independently operated by coupling terminals to a source and a gate for each transistor and the shared drain. Characteristics of the two transistors can be controlled by adjusting feature sizes, such as overlap between the gate and the shared drain for a transistor. In particular, two transistors with different voltage requirements can be manufactured using a shared drain structure, which can be useful in amplifier circuitry and in particular Class-D amplifiers.

Dual device semiconductor structures with shared drain

A method for calculating a calibration gain used for common-mode rejection in a current sensing system may include measuring a first value of a common-mode voltage associated with the current sensing system and a first output value of the current sensing system occurring at the first value of the common-mode voltage, measuring a second value of the common-mode voltage associated with the current sensing system and a second output value of the current sensing system occurring at the second value of the common-mode voltage, and based on a difference between the second output value of the current sensing system and the first output value of the current sensing system and a difference between the second value of the common-mode voltage and the first value of the common-mode voltage, calculating the calibration gain.

Calibration of current sense amplifier with common-mode rejection

A system may include a charge pump configured to transfer electrical energy from a source of electrical energy coupled to an input of the charge pump to an energy storage device coupled to an output of the charge pump and configured to store the electrical energy transferred from the source of electrical energy, a power converter configured to transfer electrical energy from the energy storage device to an output of the power converter, wherein the power converter comprises a first plurality of switches and a power inductor arranged such that one switch of the first plurality of switches is coupled between the power inductor and the output of the charge pump, an output stage configured to transfer electrical energy between the output of the power converter to a load coupled to an output of the output stage, the output stage comprising a second plurality of switches, and a controller configured to generate an output voltage at the output of the output stage as an amplified version of an input signal.

High efficiency transducer driver

A dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) may include a MOSFET having a channel region, a drain, and a source, a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region.

Dual gate metal-oxide-semiconductor field-effect transistor

A system may include a charge pump configured to operate in a plurality of modes including a first mode in which the ratio of an output voltage to an input voltage of the charge pump is a first ratio and a second mode in which the ratio is a second ratio and a controller configured to limit current flowing between a power source of the charge pump to the charge pump, wherein the power source provides the input voltage, by limiting a transfer of charge between the power source and the charge pump during a switching cycle of the charge pump responsive to a change in operation between modes of the plurality of modes.

Charge pump input current limiter

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Austin, TX, United States of America

Christian Larsen