Advanced Micro Devices Corporation

Infineon Technologies Ag

Globalfoundries Inc.

Christian Krueger

Hans-Joachim Schulze

Manfred Horstmann

Karsten Wieczorek

Thomas Feudel

Moriz Jelinek

Volker Grimm

Zhiyong Zhao

Niels-Wieland Hauptmann

Stephan Kronholz

Peter Javorka

Werner Schustereder

Maciej Wiatr

Roman Boschke

Daniel Schloegl

Benedikt Stoib

Oana Julia Spulber

Lutz Herrmann

Thomas Waechtler

Lutz Eckart

Rastislav Kocis

Marek Braun

Michael Kokot

Heinz Seidel

Thomas Beck

Bernd Bitnar

A semiconductor device includes: an n-doped drift region between first and second surfaces of a semiconductor body; a p-doped first region at the second surface; and an n-doped field stop region between the drift and first region. The field stop region includes first and second sub-regions with hydrogen related donors. A p-n junction separates the first region and first sub-region. A concentration of the hydrogen related donors, along a first vertical extent of the first sub-region, steadily increases from the pn-junction to a maximum value, and steadily decreases from the maximum value to a reference value at a first transition between the sub-regions. A second vertical extent of the second sub-region ends at a second transition to the drift region where the concentration of hydrogen related donors equals 10% of the reference value. A maximum concentration value in the second sub-region is at most 20% larger than the reference value.

Semiconductor device including a field stop region

A method of manufacturing a semiconductor device includes reducing a thickness of a semiconductor substrate and/or forming a doped region in the semiconductor substrate. The method further includes changing an ion acceleration energy of an ion beam while effecting a relative movement between the semiconductor substrate and the ion beam impinging on the semiconductor substrate.

Method of manufacturing a semiconductor device by using ion beam technique

In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.

Reduction of defect rates in PFET transistors comprising a Si/Ge semiconductor material formed by epitaxial growth

By operating an implantation tool with a source gas having a halogen fraction of 66 atomic percent or less relative to the total composition of the source gas, an in situ cleaning effect may be achieved while performing an implantation process.

Method of implanting ion species into microstructure products by concurrently cleaning the implanter

Resist masks exposed to high-dose implantation processes may be efficiently removed on the basis of a combination of a plasma-based etch process and a wet chemical etch recipe, wherein both etch steps may include a highly selective etch chemistry in order to minimize substrate material loss and thus dopant loss in sophisticated semiconductor devices. The first plasma-based etch step may provide under-etched areas of the resist mask, which may then be efficiently removed on the basis of the wet chemical etch process.

Technique for removing resist material after high dose implantation in a semiconductor device

Disclosed herein are various methods of determining characteristics of doped regions on device wafers, and a system for accomplishing same. In one illustrative embodiment, the method includes providing a device substrate comprising a plurality of masked areas, a plurality of unmasked areas, and at least one doped region formed in the substrate, determining a ratio between the unmasked areas and the masked areas for the device substrate, illuminating an area of the device substrate comprising the masked areas, the unmasked areas, and at least one doped region, and measuring an induced surface photovoltage of the device substrate while accounting for the ratio of the unmasked areas and the masked areas of the device substrate. In another illustrative embodiment, the method includes providing an SOI substrate comprised of an active layer, the active layer having a thickness, illuminating an area of the substrate using a light source having a wavelength that is sufficiently long such that an excited region created in the active layer due to the illumination does not extend beyond the thickness of the active layer, and measuring an induced surface photovoltage resulting from the illumination.

Methods of determining characteristics of doped regions on device wafers, and system for accomplishing same

The present invention provides an improved Faraday cup configuration that allows determination of a non-zero angle of incidence and/or a beam divergence with high accuracy. Moreover, by substantially simultaneously and continuously displaying information of a plurality of Faraday cups, the set-up of an implantation tool may be significantly facilitated and may be carried out in a substantially automated manner.

Advanced ion beam detector for ion implantation tools

When changing a dopant species in an implantation tool, typically a clean process is performed to reduce cross-contamination, which is considered a major issue in implant cycles applied in advanced CMOS processes. Especially, the employment of an implanter previously used for heavy ions may generate increased cross-contamination when subsequently used for boron or phosphorus implants at moderate energies. A clean implant process using xenon gas may effectively reduce this cross-contamination at shorter process times compared to a conventional argon clean step.

Method of reducing contamination-induced process variations during ion implantation

In manufacturing a recessed gate transistor, a channel implantation and a source/drain implantation are performed by means of a single implantation mask prior to the formation of a gate opening. Thereafter, the gate opening is formed to a depth that extends substantially to the channel implant so that raised drain and source regions are created which are substantially even with the gate electrode formed in the gate opening. Consequently, expensive and complex epitaxial growth steps can be avoided.

Methods of forming a transistor having a recessed gate electrode structure

An array of high aspect openings enables fast and accurate measurement of incidence angle deviation and/or beam divergence. The high aspect ratio assures that only ions of a predefined small incidence angle range may reach a conductive detection surface, thereby allowing efficient control of the ion beam parallelism by maximizing the beam current through the high aspect ratio openings. Moreover, if the array of openings is provided with individual beam current measurement points, spatially resolved intensity measurements may be performed that allow estimation of the beam shape. Thus, a movable Faraday cup assembly may be replaced with the stationary array of high aspect ratio openings, thereby improving tool reliability.

Advanced ion beam measurement tool for an ion implantation apparatus

An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

SOI field effect transistor element having a recombination region and method of forming same

A manufacturing process for fabricating field effect transistors is disclosed comprising the generation of a strained surface layer on the surface of the substrate on which the transistor is to be fabricated. The strained surface layer is generated by implanting xenon and/or other heavy inert ions into the substrate. Implantation can be performed both after or prior to the gate oxide growth. The processing afterwards is carried out as in conventional MOS technologies. It is assumed that the strained surface layer improves the channel mobility of the transistor.

Semiconductor device having an improved strained surface layer and method of forming a strained surface layer in a semiconductor device

Test wafer consumption is a significant contributor to overall cost of manufacturing in semiconductor industry due to scrapping the test wafers after one monitoring of implantation parameters. This invention provides a method to reuse the same test wafer for monitoring the implantation parameters more than once. This method comprises the possibility of implanting the same implant species together with identical implanting and annealing conditions as well as of implanting a broad variety of implant species together with varying implanting and annealing conditions. Therefore, this invention helps to significantly reduce the number of test wafers consumed in the implant-area.

Growing community of inventors

Liegau-Augustusbad, Germany

Christian Krueger