Hewlett-packard Company

Christian J Warling

Lawrence Nathaniel Taugher

Kerry J Monroe

James G Wendt

Erik R Habbinga

Mark C Lucas

William P Repasky

Steven G Hall

Eric McLaughlin

Brian Michael Dowling

Thomas L Bloom

A fly-by checksum is generated at a lower layer of the protocol stack and travels up to a high layer of a protocol stack to verify incoming data. In one embodiment, a network adapter comprises includes one or more protocol stacks and a LAN controller that includes a fly-by checksum generation unit. A checksum algorithm is registered with the fly-by checksum generation unit for each protocol layer that is to receive a fly-by checksum. As an incoming packet is transferred from network media to network adapter memory, the fly-by checksum generation unit calculates a fly-by checksum for each checksum algorithm that has been registered. After the fly-by checksums are complete, they are transmitted to the network adapter memory and are transmitted up the appropriate protocol stack within a checksum channel. When data reaches a layer of the protocol stack for which the fly-by checksum was generated, the fly-by checksum is removed from the checksum channel and is used to verify the integrity of the data.

Hardware checksum assist for network protocol stacks

A network node includes a serial physical sublayer (PHY) chip, a parallel PHY chip, and a media access control (MAC) chip. The serial physical sublayer chip, includes a single bit transmit data input, a single bit receive data output, and serial PHY control signal input/output (I/O) lines. The parallel PHY chip includes a multi-bit transmit data input, a multi-bit receive data output, and parallel PHY control signal I/O lines. The MAC chip includes a multi-bit transmit data output, a multi-bit receive data input and parallel control signal I/O lines. The multi-bit transmit data output is connected to the multi-bit transmit data input. One bit of the multi-bit transmit data output is connected to the single bit transmit data input. The multi-bit receive data input is connected to the multi-bit receive data output. One bit of the multi-bit receive data input is connected to the single bit receive data output. The parallel control signal I/O lines are connected to the parallel PHY control signal I/O lines. A subset of the parallel control signal I/O lines are connected to the serial PHY control signal I/O lines.

Media access controller capable of connecting to a serial physical layer device and a media independent interface (MII) physical layer device

A digital line driver circuit with active pull-down, high transient pull-up current, and limited steady-state pull-up current. Steady-state pull-up current is provided through a pull-up resistor. Transient pull-up current is provided by a capacitively coupled active pull-up circuit.

Logic output circuit with high transient pull-up current

Growing community of inventors

Rocklin, CA, United States of America

Christian J Warling