Infineon Technologies Ag

Christian Herzum

Martin Wurzer

Alfons Dehe

Stefan Barzen

Michael Kropfitsch

Roland Helm

Wolfgang Hartung

Carsten Ahrens

Wolfgang Klein

Ulrich Krumbein

Reinhard Losehand

Stefan Pompl

Hubert Werthmann

Jakob Huber

Klaus Diefenbeck

Karlheinz Mueller

Michael Schrenk

Bernd Eisener

Karl-Heinz Mueller

Raimund Peichl

Karlheinz Müller

Ulf Bartl

Cartens Ahrens

Angelika Geiselbrechtinger

A packaged MEMS device and a method of calibrating a packaged MEMS device are disclosed. In one embodiment a packaged MEMS device comprises a carrier, a MEMS device disposed on the substrate, a signal processing device disposed on the carrier, a validation circuit disposed on the carrier; and an encapsulation disposed on the carrier, wherein the encapsulation encapsulates the MEMS device, the signal processing device and the memory element.

Packaged MEMS device comprising adjustable ventilation opening

A MEMS device and a method of making a MEMS device are disclosed. In one embodiment a semiconductor device comprises a substrate, a moveable electrode and a counter electrode, wherein the moveable electrode and the counter electrode are mechanically connected to the substrate. The movable electrode is configured to stiffen an inner region of the movable membrane.

MEMS device and method of making a MEMS device

Packaged MEMS device and method of calibrating a packaged MEMS device

A tunable MEMS device and a method of manufacturing a tunable MEMS device are disclosed. In accordance with an embodiment of the present invention, a semiconductor device comprises a substrate, a moveable electrode and a counter electrode. The moveable electrode or the counter electrode comprises a first region and a second region, wherein the first region is isolated from the second region, wherein the first region is configured to be tuned, wherein the second region is configured to provide a sensing signal or control a system, and wherein the moveable electrode and the counter electrode are mechanically connected to the substrate.

Tunable MEMS device and method of making a tunable MEMS device

The invention relates to an overvoltage protection apparatus having a semiconductor substrate, a first doping region in order to provide a protection diode, and a second doping region in order to provide a protection resistance, with the second doping region being immediately adjacent to the first doping region.

Overvoltage protection apparatus and an associated protection circuit

An electronic device includes a substrate, an insulating layer arranged on the substrate, the insulating layer having an opening in an area of the surface of the substrate, an active layer arranged within the opening on the surface of the substrate, the active layer including a guard ring in those areas of the surface and of the active layer which are adjacent to the insulating layer, and a contacting layer arranged on an area of the active layer, the contact layer being adjacent to an area of the guard ring. The device may be produced by a process of three-fold self-alignment, to be precise utilizing a spacer process by means of which a diffusion source having a lateral extension far below the lithography limit is made possible.

Electronic device with guard ring

The invention relates to a method for generating very short gate structures. In a method for generating a structure on a substrate in accordance with one embodiment of the invention, first of all a layer sequence of a first oxide layer, a first nitride layer and a second oxide layer is disposed onto the substrate. Subsequently, a portion of the second oxide layer and a portion of the first nitride layer is removed in order to expose a portion of the first oxide layer. Then, a part of the first nitride layer above the first oxide layer and below the second oxide layer is removed in order to expose the area of the structure.

Method for generating a structure on a substrate

A capacitor includes a semiconductor substrate in which a trench is formed through which the substrate is doped. A dielectric layer covers the surface of the trench, wherein furthermore an electrically conductive material is arranged in the trench. A first contact structure for contacting the electrically conductive material in the trench in an electrically conductive manner and a second contact structure for contacting the doped semiconductor substrate in an electrically conductive manner are also formed in the capacitor. The capacitor has low series resistance of the electrodes and may be produced in a simple manner.

Capacitor and method for producing a capacitor

In a method for creating a stepped structure on a substrate, which at least includes a first portion with a first thickness and a second portion with a second thickness, at first a layer sequence of a first oxide layer, a first nitride layer, and a second oxide layer is applied onto the substrate. Then a portion of the second oxide layer and a portion of the first nitride layer are removed to expose a portion of the first oxide layer. Then a part of the first nitride layer is removed to establish the first region of the stepped structure. Then the thickness of the first oxide layer is changed at least in the established first region to establish the first thickness of this region. Subsequently, a further part of the first nitride layer is removed to establish a second region of the stepped structure.

Method for creating a stepped structure on a substrate

In a method for producing a gate structure for a MOS transistor, first, a layer sequence of oxide layer, auxiliary layer and masking layer is generated on a substrate, wherein the auxiliary layer and the masking layer are patterned to determine an edge separating an area of the oxide layer covered by these layers from an exposed area thereof. Afterwards, an oxidation is performed to generate an oxide ramp in the area of the edge. Then, the auxiliary layer is partly removed to generate a hollow space of predetermined length between the oxide layer and the masking layer. A gate electrode material is introduced into the hollow space for generating a gate electrode.

Method for producing a gate structure for an MOS transistor

A semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration that is lower than a dopant concentration of the base layer, and a second layer of a second conductivity type being operative with the first layer in order to form a transition between the first conductivity type and the second conductivity type. A course of a dopant profile at the transition between the base layer and the first layer is set such that in an ESD case a space charge region shifted to the transition between the base layer and the first layer reaches into the base layer.

Semiconductor structure and method for improving its ability to withstand electrostatic discharge (ESD) and overloads

A semiconductor circuit arrangement includes a circuit element embedded in a semiconductor substrate of a first conductivity type in an integrated manner and is provided with at least one gate electrode and first and second terminal electrodes. The first terminal electrode includes a well region that is embedded in the semiconductor substrate and is of a second conductivity type which is opposite the first conductivity type. A sub-well region is embedded in the well region of the first terminal electrode and is of the second conductivity type and has a higher doping than said well region. The sub-well region is embedded in the surface of the substrate and ends without reaching a well region of the gate electrode which is of the first conductivity type.

Growing community of inventors

Starnberg, Germany

Christian Herzum