Telefonaktiebolaget Lm Ericsson (publ)

Christian Elgaard

Lars Sundström

Henrik Sjöland

Stefan Mikael Andersson

Imad Ud Din

Janne Peltonen

Anna-Karin Stenman

Magnus Åström

Fredrik Tillman

Andreas Axholt

Staffan Ek

Mohamed Hamid

Anna Karin Stenman

Florent Torres

Ali Al-Qamaji

Fida Abdalrahman

Magnus ÅSTRÖM

Stefan Andersson

A differential transceiver switch circuitry having an antenna port, a positive and a negative receiver port, a first positive and a first negative amplifier port and at least one second positive and negative second amplifier port. The differential transceiver switch circuitry is configured to operate in a reception mode to allow reception signals at the antenna port to be transferred to the positive and negative receiver port and in a transmission mode to allow transmission signals at the first positive and first negative amplifier port and at the second positive and second negative amplifier port to be transferred to the antenna port. The differential transceiver switch circuitry has a transmit arrangement and a receive arrangement having receiver switch circuitry configured to prevent transmission signals from entering the receive arrangement in the transmission mode.

Differential transceiver switch circuitry

The present invention relates inter alia to a transmitter arrangement (), in particular for radio communication, comprising at least two antenna elements (), spaced apart by a defined distance and a differential output amplifier () with a first output () coupled to a first () of the at least two antenna elements () and with a second inverted output () coupled to a second () of the at least two antenna elements (). A first transmission line element () is arranged between at least one of the first and second outputs () and the respective one of the at least two antenna elements () and is configured such that signals applied to respective input taps () of the at least two antenna elements () are substantially in-phase with each other.

Transmitter arrangement, transceiver, radio communication system and method

Transceiver switch circuitry having an antenna port, a receiver port and two transmitter ports. The transceiver switch circuitry is configured to be operable in a reception mode to allow reception signals at the antenna port to be forwarded to the receiver port, and in a transmission mode to allow transmission signals, having a center frequency with a wavelength λ, at the first transmitter port and the second transmitter port to be forwarded to the antenna port for transmission. The transceiver switch circuitry includes a receive arrangement comprising having a receiver λ/4 impedance transformer and a receiver switch circuitry configured to ground the first λ/4 impedance transformer at the receiver port in the transmission mode; and a transmit arrangement having three transmitter impedance transformers and a first and second transmitter switch circuitry configured to virtually ground a second side of the first λ/4 impedance transformer in the reception mode.

Transceiver switch circuitry

A bias circuit for a PA. A first transistor has its drain terminal and its gate terminal connected to a first circuit node and its source terminal connected to a first supply terminal, a first current source connected to the first circuit node, and a first resistor connected between the first and second circuit nodes. A second transistor receives a first component of a differential input signal to the PA at its gate terminal, has its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal, and a third transistor receives a second component of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal. The gates terminals of the second and third transistors are biased by a first voltage.

Bias circuit and power amplifier circuit

A transmitter circuit has a signal input for receiving an analog input signal and a local oscillator (LO) input for receiving an LO signal. A mixer circuit has a first input, a second input, and an output. The second input of the mixer circuit is connected to a signal input of the transmitter circuit. A PA circuit has an input connected to the output of the mixer circuit, and an output. A control circuit generates a phase-control signal and a gain-control signal in response to an envelope of the analog input signal. A phase-control circuit generates a phase-adjusted LO signal in response to the LO signal and the phase-control signal and supplies the phase-adjusted LO signal to the first input of the mixer circuit. A gain-control circuit controls a gain of the transmitter circuit in response to the gain-control signal.

Transmitter circuit

A bias circuit for a PA. A first transistor has its drain terminal and its gate terminal connected to a first circuit node and its source terminal connected to a first supply terminal, a first current source connected to the first circuit node, and a first resistor connected between the first and second circuit nodes. A second transistor receives a first component of a differential input signal to the PA at its gate terminal, has its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal, and a third transistor receives a second component of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal. The gates terminals of the second and the third transistors are biased by a first voltage.

An electronic device comprises a first feedback circuit operatively connected to an amplitude detector and a first control input of an oscillator. The first feedback circuit is configured to control an amplitude of an output of the oscillator by continuously applying a first control signal to the first control input in response to an amplitude detected by the amplitude detector. The electronic device further comprises a second feedback circuit operatively connected to the amplitude detector and a second control input of the oscillator. The second feedback circuit is configured to modify one or more amplitude regulating parameters of the oscillator by providing a second control signal in response to the amplitude being beyond an upper or lower amplitude threshold, and refrain from modifying the one or more amplitude regulating parameters when the amplitude is within the upper and lower amplitude thresholds.

Low-noise oscillator amplitude regulator

An interleaved antenna array configuration in a radio node is disclosed. The antenna array includes a mixture of isolated and non-isolated antenna elements interleaved in each row and each column of the antenna array. Each isolated antenna element is only adjacent to one or two non-isolated antenna elements in each row and each column. Each non-isolated antenna element is only adjacent to one or two isolated antenna elements in each row and each column. By interleaving the isolated and non-isolated antenna elements in each row and column of the antenna array, it is possible to reduce a number of antenna isolators, thus helping to reduce cost and footprint of the radio node. Further, by using a combination of antenna isolators and simplified digital pre-distortion (DPD) actuators in association with the interleaved antenna array, the radio node is able to satisfy stringent radio frequency (RF) performance requirements.

Interleaved antenna array configuration in a radio node

A frequency generation solution controls an oscillator amplitude using two feedback paths to generate high frequency signals with lower power consumption and lower noise. A first feedback path provides continuous control of the oscillator amplitude responsive to an amplitude detected at the oscillator output. A second feedback path provides discrete control of the amplitude regulating parameter(s) of the oscillator responsive to the detected oscillator amplitude. Because the second feedback path enables the adjustment of the amplitude regulating parameter(s), the second feedback path enables an amplifier in the first feedback path to operate at a reduced gain, and thus also at a reduced power and a reduced noise, without jeopardizing the performance of the oscillator.

An oscillator circuit comprises a crystal oscillator arranged to generate an oscillation signal, a bias current generator arranged to supply a bias current to the crystal oscillator, and a feedback stage arranged to generate a feedback signal in response to an amplitude of the oscillation signal reaching an amplitude threshold. The bias current generator is arranged to: in response to a supply of power to the oscillator circuit being switched on, generate the bias current at an increasing level commencing from a first level; in response to the feedback signal, terminate the increasing; and during subsequent oscillation of the crystal oscillator, supply the bias current at a second level dependent on a final level of the bias current reached when the increasing is terminated.

Oscillator circuit with bias current generator

An integrated transformer arrangement for combining output signals of multiple differential power amplifiers to a single-ended load. The integrated transformer arrangement comprises a first transformer branch comprising an inductor loop. The inductor loop comprises a set of N windings connected in series. The first transformer branch further comprises a number of primary inductors. Each primary inductor comprises a winding placed concentrically to one winding of the inductor loop, and each primary inductor is configured to couple to a differential output of one of the multiple differential power amplifiers. The integrated transformer arrangement further comprises a secondary inductor comprising a winding placed concentrically to a winding of the inductor loop, and the secondary inductor is configured to couple to the single-ended load.

Integrated transformer

A power amplifier arrangement comprises a power amplifier comprising at least one transistor having a first gate and a second gate. The first gate is configured to receive a radio frequency input signal superimposed with a first control signal, and the second gate is configured to receive a second control signal. The first control signal is a linearization signal varying in relation to an envelope of the input signal and the second control signal is a temperature compensation signal varying in relation to a temperature of the power amplifier, or vice versa.

Power amplifier arrangement

A power amplifier, for a transmitter circuit is disclosed, which comprises at least one field-effect transistor having a gate terminal and a bulk terminal. The at least one field-effect transistor is configured to receive an input voltage at the gate terminal and a dynamic bias voltage at the bulk terminal. The power amplifier comprises a bias-voltage generation circuit configured to generate the dynamic bias voltage as a nonlinear function of an envelope of input signal. The input voltage is a linear function of the input signal. The bias-voltage generation circuit comprises a rectifier circuit configured to generate a rectified input voltage and an amplifier circuit, operatively connected to the rectifier circuit, configured to generate the dynamic bias voltage based on the rectified input voltage. The amplifier circuit is a variable-gain amplifier circuit and the power amplifier comprises a control circuit configured to tune the gain of the amplifier circuit.

Power amplifier

An integrated circuit (-) is disclosed, which is configured to be connected to an antenna module () having multiple antenna elements (). The integrated circuit (-) comprises a plurality of communications circuits (), each of which is configured to be connected to an antenna element () of the antenna module (). It also comprises a first clock input terminal () configured to receive a reference clock signal from outside the integrated circuit (-) and a first clock-distribution network () connected between the first clock input terminal () and a first subset () of the communication circuits (). Furthermore, it comprises a second clock input terminal () configured to receive a reference clock signal from outside the integrated circuit (-) and a second clock-distribution network () connected between the second clock input terminal () and a second subset () of the communication circuits ().

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Lund, Sweden

Christian Elgaard