Infineon Technologies Ag

National Semiconductor Germany Ag

Bayerische Motoren Werke Aktiengesellschaft

Gm Global Technolgoy Operations, Inc.

Robert Boschgmbh

Daimler Chrysler Ag

Xignal Technologies Ag

Other

Koninklijke Philips Corporation N.v.

Motorola Corporation

Freescale Semiconductor,inc.

Nxp B.v.

National Semiconductor Corporation

Christian Ebner

Andreas Wiesbauer

Christian Jenkner

Ernesto Romani

Stephan Mechnig

Joseph Hufschmitt

Florian Hartwich

Thomas M Forest

Peter Fuhrmann

Robert Hugel

Florian Bogenberger

Manfred Bruno Zinke

Christopher Temple

Bernd Elend

Martin Peller

Josef Berwanger

Mathias Rausch

Bernd Müller

Harald Eisele

Arnold W Millsap

Anton Schedl

Gerhard Mitteregger

Ralf Belschner

Jörn Ungermann

Bernd Hedenetz

Harald Weiler

Peter Lohrmann

Thomas Führer

Thomas Wuerz

Patrick Willem Heuts

Matthias Kühlewein

Dietmar Straeussnigg

Robert J Disser

Patrick Allen Mescher

Elmar Bach

Scott Alan Millsap

Bernd Schafferer

Matthias Friedrich Herrmann

Brian Thomas Murray

Benno Muehlbacher

Athanasios Kollias

Heinz Werker

Francesco Polo

Michael D Byers

Markus Hamm

Georgi Nikolov Panov

Jipeng Li

Jeffrey Heinrichs

Hendrikus T Smakman

Christoph Platz

Detlef Krukenkamp

Johannes Hohl

Schedl Anton

Michael Gr&auml;f

Kai-Uwe Balszuweit

Slawomir Bakaus

Markus Krug

J&uuml;rgen Guldner

A method for controlling a recuperation device that converts kinetic energy into electric energy in a vehicle is provided. The method includes the acts of actuating at least one actuation element for generating a braking action, at least briefly arranging the actuated actuation element in at least one predefined first trigger position, and activating the recuperation device in a defined functional scope in response to the brief arrangement of the actuated actuation element in the at least one predefined first trigger position.

Method for controlling a recovery device of a vehicle

In accordance with an embodiment, a method of performing a measurement with a capacitive sensor includes generating a periodic excitation signal that includes a series of pulses and smoothing edge transitions of the series of pulses to form a shaped periodic excitation signal that includes a flat region between the smoothed edge transitions. The method further includes providing the shaped periodic excitation signal to a first port of the capacitive sensor and measuring a signal provided by a second port of the capacitive sensor.

System and method for a capacitive sensor

An embodiment includes a method of performing a measurement using a micro-electro-mechanical system (MEMS) device that includes a plurality of MEMS sensors having different resonant frequencies. The method includes applying an excitation signal to a first port of the MEMS device such that each of the plurality of the MEMS sensors is stimulated by the excitation signal. The method further includes measuring a signal at a second port of the MEMS device and determining a measured value based on the measuring the signal.

System and method for a MEMS sensor

According to an embodiment, a sensor circuit includes a sigma-delta analog to digital converter (ADC), a dithered clock coupled to the sigma-delta ADC, and a supply voltage circuit coupled to the sigma-delta ADC. The sigma-delta ADC is configured to be coupled to a low frequency transducer, and the dithered clock is configured to control of the sigma-delta ADC based on a dithered clock signal.

A measurement method includes generating, by a sensor, a response signal in response to an excitation signal. The method also includes generating a sampling clock signal in accordance with a pseudo-random jitter, and sampling the response signal in accordance with the sampling clock signal to determine a plurality of digital samples. The method also includes combining the plurality of digital samples to form a measurement sample.

In accordance with an embodiment of the present invention, a method of operating a voltage generator includes providing a bypass switch to bypass a ripple filter coupled to a power converter. A coupling capacitor includes a first plate and a second plate. The first plate is coupled to a control node of the bypass switch. A bypass control signal is received. The control node of the bypass switch is toggled between a first voltage to a second voltage different from the first voltage by toggling the second plate of the coupling capacitor based on the bypass control signal.

Voltage generator and biasing thereof

A microphone or a microphone sensor system operates with a sensor interface that receives a supply voltage at a supply terminal. The sensor interface detects a command at the supply terminal based on a change in the supply voltage and communicates the command or data related to the command to a component of the sensor system. The supply terminal is a bidirectional terminal that further communicates data related to the sensor system via the supply terminal.

Microphone configuration and calibration via supply interface

In one embodiment, digital-to-analog converter (DAC) circuit includes dual DAC units employing pseudo-return-to-zero DAC operations to reduce inter-symbol interference. Moreover, each DAC unit is implemented using complementary MOS transistors to improve conversion performance. In another embodiment, a DAC calibration scheme performs background calibration of an array of DAC circuits in continuous time using a reference DAC circuit and a spare DAC circuit. Calibration (also referred to as 'trimming') of the DAC circuit using the calibration scheme of the present invention ensures that the DAC operates with high linearity over process variations. In one embodiment, the DAC circuit and the DAC calibration scheme are applied as the feedback DAC in a continuous-time sigma-delta (CT-&#x3a3;&#x394;) analog-to-digital converter to realize high performance and high precision analog-to-digital conversions.

DAC circuit with pseudo-return-to-zero scheme and DAC calibration circuit and method

The present invention concerns a digital phase detector (PD) and also a method for digital phase detection, as can in particular be used e.g. in a so-called phase locked loop (PLL). According to the invention a digital phase detection signal (PD_OUT) is obtained, which specifies the phasing of an input clock signal (PD_IN) with reference to a higher frequency sampling clock signal (CK). In order hereby to overcome the limitation of the phase resolution as a result of a limited performance capability, in particular limited speed of the electronic components of a sampling device (), a new kind of concept is used, in which the sampling clock signal (CK) is not immediately used for sampling (), but is subjected beforehand to a digitally adjustable phase displacement (). There originates an 'auxiliary sampling clock signal' (CK&#x3c;&#x3e;). The sampling () delivers a first, more significant digital component (OUT&#x3e;) of the phase detection signal (PD_OUT). Based on an evaluation of this first digital component (OUT&#x3e;) a phase displacement () is undertaken and a second digital component (OUT&#x3e;) of the phase detection signal (PD_OUT) is generated. The auxiliary sampling clock signal (CK&#x3c;&#x3e;) is here adjustable in steps, which in each case are smaller than one period of the sampling clock signal (CK).

Digital phase detector and a method for the generation of a digital phase detection signal

The invention refers to a method for monitoring a communication media access schedule of a communication controller () of a communication system () by means of a bus guardian (). The communication system () comprises a communication media () and nodes () connected to the communication media (). Each node () comprises a communication controller () and a bus guardian () assigned to the communication controller (). Messages are transmitted among the nodes () across the communication media () based on a cyclic time triggered communication media access scheme. In order to provide a mechanism which allows the bus guardian () to monitor the communication media access scheme of the communication controller () even during startup of the communication it is suggested, that the bus guardian () has a priori knowledge about possible deviations from the communication media access schedule during startup of the communication and that the bus guardian () during startup makes use of the a priori knowledge to distinguish between an allowed deviation and a forbidden deviation caused by a failure of the communication controller ().

Method for monitoring a communication media access schedule of a communication controller of a communication system

The invention relates to the generation of an electric output signal with a specified frequency and a phase (P) dependent upon a control signal (x) by means of weighted superposition of several input signals (s, s, s, s), which have the specified frequency but different input signals phases, whereby the weighted superposition is applied to a parallel switching of adjustable transconductance stages which are each adjusted by the control signal (x) and to each of which one of the input signals (s, s, s, s) is supplied. In order to be able to use this so-called phase interpolation to meet higher linearity requirements, the invention provides that for the generation of the output signal with a phase which lies between a first input signal phase (0&#xb0;) of a first input signal (s) and a second input signal phase (120&#xb0;) of a second input signal (s) which second phase is larger by a phase difference (120&#xb0;), the first input signal (s) and the second input signal (s) and two further input signals (s, sand S, sresp.) are superimposed in a weighted fashion, whereby the two further input signals (s, sand S, sresp.) have phases different by the phase difference (120&#xb0;) and are phase-shifted by one half (60&#xb0;) of the phase difference with regard to the first and second input signals (s, s).

Method and circuit arrangement for generating a periodic electric signal with controllable phase

An amplifier is described which amplifies an input signal according to a defined amplification factor, and which generates an output signal. To reduce an offset fraction of the output signal the amplifier comprises a feedback path which has lowpass characteristics and which returns the output signal in a lowpass-filtered state to an input of the amplifier. The feedback path comprises an amplifier stage as well as at least one Miller capacitance connected between an input and an output of the amplifier stage.

Amplifier with low pass filter feedback

It is an object of the present invention to provide an amplifier circuit that supplies a differential output signal (Voutp&#x2212;Voutn) with a stable common mode potential (&#xbd;&#xd7;(Voutp+Voutn)) and a stable amplification characteristic. An essential feature of the invention is a control path () feeding back into a control stage of the amplifier circuit for the combined control of the quiescent currents that flow through the output transistors (T-T), and of the common mode potential of the differential output signal. By means of this combination of two control functions in one and the same control path () any coupling between separate control loops is avoided.

Class AB amplifier circuit with combined quiescent current and common mode control

A method and a bit stream decoding unit for bit stream decoding has a bit stream comprising a number of consecutive samples. In order to provide for rapid and, in particular, reliable decoding of the bit stream, a detection window comprising a number of samples is defined and the detection window is positioned at certain positions on the bit stream in order to comprise certain samples with respective sample values. A majority voting is applied to the sample values in the detection window and, in dependence on the result of the majority voting, the bit stream is decoded and respective bit values are generated.

Method and bit stream decoding unit using majority voting

The invention relates to a continuous-time delta-sigma analog digital converter () for converting an analog input signal (IN) to a digital output signal (OUT), comprising an analog filter (), which filters the analog input signal, a quantifier () cycled by a clock signal (CLK), which quantifier quantifies the filtered analog signal transmitted by the analog filter () to generate the digital output signal, and a feedback device () with at last one digital analog converter, which transmits at least one analog feedback signal based on the digital output signal (OUT) to the analog filter (). To simplify the feedback without adversely affecting the converter stability and power consumption, provision is made, according to the invention, for the feedback device () for generating a feedback signal corresponding to the differentiated output signal of the quantifier, to comprise two digital analog converters (--) to which the digital output signal (OUT) of the quantifier () is transmitted via a delay stage (--) with different delays, and hose analog output signals are transmitted to an analog subtractor (-).

Continuous-time delta-sigma analog digital converter

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Munich, Germany

Christian Ebner