Infineon Technologies Ag

Intel Corporation

Intel Mobile Communications Gmbh

Indian Institute of Science

International Business Machines Corporation

Samsung Electronics Co., Ltd.

Imec Vzw

Intel Deutschland Gmbh

Christian Cornelius Russ

Harald Gossner

Mayank Shrivastava

Thomas Schulz

Gernot Langguth

Wolfgang Soldner

Kai Esmark

David Alvarez

Gabriel-Dumitru Cretu

Filippo Magrini

Christian Pacha

Jens Schneider

Klaus Schruefer

Gerhard Knoblinger

Snezana Jenei

Milova Paul

Bernhard Stein

Gunther Lehmann

Krzysztof Domanski

Klaus Von Arnim

Franz Ungar

Kiran V Chatty

Franz Kuttner

Martin Streibl

Michael Mark

Eric Pihet

Martin Wendel

Markus Eckinger

Werner Hoellinger

Michael Fulde

Nirmal Chaudhary

Steven Thijs

Luis Giles

Jürgen Fehle

Mirko Scholz

Tomasz Biedrzycki

Krysztof Domanski

Bong Jae Kwon

David Trémouilles

Anton Boehm

B Sampath Kumar

Giuseppe Curello

Luis F Giles

An ESD protection circuit includes a silicon controlled rectifier (SCR) including a first conduction path between a first node and a second node and a clamp circuit coupled to a control terminal of the SCR. The clamp circuit is part of a second conduction path between the first node and the second node. During an ESD event, the clamp circuit conduct an ESD current until a threshold IV point is reached. The clamp circuit triggers the SCR, which then acts as a snapback device to conduct the ESD current at a lower voltage.

ESD protection circuit

The described techniques address issues associated with electrostatic discharge (ESD) protection for multi-die integrated circuits (ICs). The techniques include the use of two or more semiconductor dies within a multi-die IC, which may include a first semiconductor die without ESD protection but with full ESD exposure. The first semiconductor receives ESD protection via a second semiconductor die that is integrated as part of the same package with the first semiconductor die. The second semiconductor die may be electrically more remote from ESD-exposed pins compared to the first semiconductor die. The first semiconductor die may include integrated passive devices. The second semiconductor die enables ESD protection for both semiconductor dies in the same integrated IC package.

ESD protection for multi-die integrated circuits (ICs) including integrated passive devices

A silicon-controlled rectifier includes a semiconductor body including a first main surface, an active device region, a first, a second, a third and a fourth surface contact area at the first main surface and arranged directly one after another along a first lateral direction, wherein the semiconductor body is electrically contacted at each of the first to fourth surface contact areas, and a first, a second, a third and a fourth SCR region, wherein the first and third SCR regions are of a first conductivity type and directly adjoin the first and third surface contact areas, respectively, and wherein the second and fourth SCR regions are of a second conductivity type and directly adjoin the second and fourth surface contact areas, respectively, wherein the first SCR region is electrically connected to the fourth SCR region, and the second SCR region is electrically connected to the third SCR region.

Silicon controlled rectifier

In accordance with an embodiment, a semiconductor device includes: an n-doped region disposed over an insulating layer; a p-doped region disposed over the insulating layer adjacent to the n-doped region, where an interface between the n-doped region and the p-doped region form a first diode junction; a plurality of segmented p-type anode regions disposed over the insulating layer, each of the plurality of segmented p-type anode regions being surrounded by the n-doped region, where a doping concentration of the plurality of segmented p-type anode regions is greater than a doping concentration of the p-doped region; and a plurality of segmented n-type cathode regions disposed over the insulating layer. Each of the plurality of segmented n-type cathode regions are surrounded by the p-doped region, where a doping concentration of the plurality of segmented n-type cathode regions is greater than a doping concentration of the n-doped region.

SCR structure for ESD protection in SOI technologies

A silicon-controlled rectifier (SCR) includes a semiconductor body including a first main surface, an active device region, a first, a second, a third and a fourth surface contact area at the first main surface and arranged directly one after another along a first lateral direction, wherein the semiconductor body is electrically contacted at each of the first to fourth surface contact areas, and a first, a second, a third and a fourth SCR region, wherein the first and third SCR regions are of a first conductivity type and directly adjoin the first and third surface contact areas, respectively, and wherein the second and fourth SCR regions are of a second conductivity type and directly adjoin the second and fourth surface contact areas, respectively, wherein the first SCR region is electrically connected to the fourth SCR region, and the second SCR region is electrically connected to the third SCR region.

A silicon-controlled rectifier (SCR) includes a semiconductor body including a first main surface and an active device region. First through fourth surface contact areas at the first main surface are arranged directly one after another along a lateral direction. The semiconductor body is electrically contacted at each surface contact area. First and third SCR regions of a first conductivity type directly adjoin the first and third surface contact areas, respectively. Second and fourth SCR regions of a second conductivity type directly adjoin the second and fourth surface contact areas, respectively. The second SCR region at least partially overlaps a first well region of the first conductivity type at the first main surface. The first SCR region at most partially overlaps the first well region at the first main surface, and is electrically connected to the second SCR region. The third SCR region is electrically connected to the fourth SCR region.

An embodiment of a silicon controlled rectifier (SCR) includes a semiconductor body, an active device region, and a device isolation region configured to electrically insulate the active device region from neighboring active device regions. First SCR regions and a second SCR region of a first conductivity type are in the active device region. A first pn-junction or Schottky junction is formed at an interface between the first SCR regions and the second SCR region. A first plurality of the first SCR regions and sub-regions of the second SCR region are alternately arranged and directly adjoin one another. A second pn-junction is formed at an interface between the second SCR region and a third SCR region of a second conductivity type. A third pn-junction is formed at an interface between the third SCR region and a fourth SCR region of the first conductivity type.

Silicon controlled rectifier and manufacturing method therefor

The present disclosure relates to a Dual Fin SCR device having two parallel fins on which cathode, anode, n- and p-type triggering taps are selectively doped, wherein one Fin (or group of parallel Fins) comprises anode and n-tap, and other Fin (or group of parallel Fins) comprises cathode and p-tap. As key regions of the proposed SCR (anode and cathode), which carry majority of current after triggering, are placed diagonally, they provide substantial benefit in terms of spreading current and dissipating heat. The proposed SCR ESD protection device helps obtain regenerative feedback between base-collector junctions of two back-to-back bipolar transistors, which enables the proposed SCR to shunt ESD current. The proposed SCR design enables lower trigger and holding voltage for efficient and robust ESD protection. The proposed SCR device/design helps offer a tunable trigger voltage and a holding voltage with highfailure threshold.

Dual fin silicon controlled rectifier (SCR) electrostatic discharge (ESD) protection device

Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.

Area-efficient and robust electrostatic discharge circuit

The present disclosure relates to a thermal management solution for ESD protection devices in advanced Fin- and/or Nanowire-based technology nodes, by employing localized nano heat sinks, which enable heat transport from local hot spots to surface of chip, which allows significant reduction in peak temperature for a given ESD current. In an aspect, the proposed semiconductor device can include at least one fin having a source and a drain disposed over a p-well or a n-well in a substrate; an electrically floating dummy metal gate disposed close to drain or hot spot over at least a portion of the at least one fin, and an electrical metal gate is disposed close to the source; and a nano-heat sink operatively coupled with the dummy metal gate and terminating at the surface of chip in which the semiconductor device is configured so as to enable transfer of heat received from the at least one fin through the dummy metal gate to the surface of the chip.

Non-planar electrostatic discharge (ESD) protection devices with nano heat sinks

The present disclosure relates to a Silicon Controlled Rectifier (SCR) in non-planar technology to provide a robust ESD protection in System on Chip employing non-planar technologies. The disclosed SCR incorporates wire or fin shaped nanostructures extending from p-type tap to cathode, from the cathode to anode, and from the anode to n-type tap to provide parallel trigger paths to prevent problem of current crowding at the base emitter junction that limits efficient turn-on in conventional SCRs. The proposed structure helps in offering lower trigger and holding voltage, and therefore very high failure currents. The disclosed SCR has sub-3V trigger and holding voltage to provide an efficient and robust ESD protection in SOCs. The proposed device also offers three times better ESD robustness per unit area. Further the proposed SCR has no added capacitive loading and is compatible with standard process flow and design rules.

Low trigger and holding voltage silicon controlled rectifier (SCR) for non-planar technologies

One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.

Tunable FIN-SCR for robust ESD protection

A semiconductor device and device arrangement including a plurality of semiconductor regions of different conductivity types and a plurality of gates which form electrically conducting paths between the semiconductor regions. The semiconductor device and device arrangement may be configured to protect against electrostatic discharge.

Semiconductor devices and arrangements including dummy gates for electrostatic discharge protection

An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height.

Electrical device and fabrication method

A semiconductor device including: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type adjacent to the first region; third and fourth semiconductor regions of the second conductivity type over or at least partially within the first semiconductor region; a fifth semiconductor region of the first conductivity type between the third and fourth semiconductor regions; a first gate over the fifth semiconductor region; sixth and seventh semiconductor regions of the first conductivity type over or at least partially within the second semiconductor region; an eighth semiconductor region of the second conductivity type between the sixth and seventh semiconductor regions; a second gate over the eighth semiconductor region; the third and seventh semiconductor regions coupled to first and second regions of the first gate, respectively, and the fourth and sixth semiconductor regions coupled to first and second regions of the second gate, respectively.

Semiconductor devices and arrangements for electrostatic (ESD) protection

Growing community of inventors

Diedorf, Germany

Christian Cornelius Russ