Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Commissariat a L'energie Atomique

Bull Sas

Christian Bernard

Yves Durand

Didier Lattard

Fabien Clermidy

Eric Guthmuller

Didier Varreau

Pamphile Koumou

Sylvie Lesmanne

Huy Nam Nguyen

Romain Lemaire

A direct memory access controller, configured to be used in a computing node of a system on chip (SoC), includes: (1) an input buffer for receiving packets of data coming from an input/output interface of the computing node; (2) a write control module for controlling writing of data extracted from each packet to a local memory of the computing node shared by at least one processor other than the direct memory access controller; and (3) an arithmetic logic unit for executing microprograms. The write control module is configured to control the execution by the arithmetic logic unit of at least one microprogram including instruction lines for arithmetic and/or logical calculation concerning only storage addresses for storing the data received by the input buffer for a reorganization of the data in the shared local memory. Optionally, at least one microprogram may be stored in a register, and at least two operating modes (e.g., restart mode and pause mode) of the at least one microprogram stored in the register may be configurable. Exemplary microprograms can (1) provide image processing parameters including sizes of columns of image blocks, (2) provide image processing parameters including numbers of successive pieces of data to be processed which are to be written to successive addresses in the shared local memory, and (3) utilize a sequential write mode and/or an absolute-offset write mode. Microprograms may be selected based on an identifier included in a header of each packet.

Direct memory access (DMA) controller, device and method using a write control module for reorganization of storage addresses in a shared local address space

A cache coherence management system includes: a set of directories distributed between nodes of a network for interconnecting processors including cache memories, each directory including a correspondence table between cache lines and information fields on the cache lines; and a mechanism updating the directories by adding, modifying, or deleting cache lines in the correspondence tables. In each correspondence table and for each cache line identified, at least one field is provided for indicating a possible blocking of a transaction relative to the cache line considered, when the blocking occurs in the node associated with the correspondence table considered. The system further includes a mechanism detecting fields indicating a transaction blocking and restarting each transaction detected as blocked from the node in which it is indicated as blocked.

System and method for managing cache coherence in a network of processors provided with cache memories

A method for dynamically controlling throughput set points from sources to targets in a network on a chip including a plurality of nodes and a plurality of links between these nodes for transmission of data packets, including for each link of the network solicited by the transmission of data packets, estimation of an available throughput margin that includes the estimation of a first margin calculated based on a maximum throughput capacity of the link; and for each emitting source of at least one data packet, the calculation and the application of an update of its throughput set point according to the estimated available throughput margins. Estimation of available throughput margin for each link includes estimation of a second margin calculated based on a maximum local absorption capacity of possible sporadic overflows of the throughput set points and its value is determined according to the first and second calculated margins.

Method for dynamically controlling throughput set points in a network on a chip, corresponding computer program and data processing device

A system for data processing with management of a cache consistency in a network of processors including cache memories, the network including plural nodes for access to a main memory interconnected with one another, a set of directories being distributed between nodes of the network, each directory including a table of correspondence between cache lines and information fields on the cache lines. The system includes a first sub-network for interconnection of the nodes with one another, implementing a first message transmission protocol providing read/write access to the directories during any passage in the corresponding nodes of a message passing through the first sub-network, and a second sub-network for interconnection of the nodes with one another, implementing a second message transmission protocol, the second protocol excluding any read/write access to the directories during any passage in the corresponding nodes of a message passing through the second sub-network.

System and a method for data processing with management of a cache consistency in a network of processors with cache memories

The invention relates to an access controller which comprises a module () for managing writing in a circular buffer (), means () for storing a first read pointer (PL) and a second write pointer (PE), a module () for managing reading in the circular buffer (), means () for blocking reading, respectively writing, means () for storing a read or write work pointer (PT) which is different from the first and second pointers (PL; PE), and means () for updating the wo: pointer (PT) according to a predetermined update logic. The predetermined update logic comprises forward or backward movements of the work pointer (PT) inside the circular buffer (), and the controller includes means for blocking the read or write work pointer if the read work pointer (PT) points outside a memory space reserved for reading or, respectively, if the write work pointer (PT) points outside a free memory space for writing.

Direct memory access controller, corresponding method and computer program

A direct memory access controller including: a transfer module that transfers data from several data sources to at least one addressee for these data, through several buffer memories each including a predetermined number of successive elementary memory locations; a read management module that reads data stored in the buffer memories and that transfers them in sequence to the addressee; and a storage module that stores read pointers associated respectively with each buffer memory, each read pointer indicating an elementary location of the buffer memory with which it is associated and in which data can be read, wherein the buffer memories are associated respectively with each data source, and for each buffer memory, the controller includes means for executing a firmware that reads data and updates a read pointer associated with this buffer memory, and for synchronising execution of the firmwares as a function of a predetermined order of data originating from buffer memories required in a data sequence to be transferred to the addressee.

Direct access memory controller with multiple sources, corresponding method and computer program

This invention relates to a system on chip for data flow type application. The system comprises a network on chip, a central controller and processing units connected to said network via associated network interfaces. A processing unit and/or its associated network interface can be configured on command from the central controller or on a command incorporated in a data packet to be processed. The network interface comprises a client module that can request a configuration server to transmit the parameters of a configuration that is unavailable in the interface. The invention also relates to a mobile terminal/ a base station comprising a base band modem implemented by such a system on chip.

System on chip with interface and processing unit configurations provided by a configuration server

A data processing method in a network on chip formed of a plurality of processors configured to communicate between one another, and at least one network controller configured to initialize communications in the network, the method including: receiving and storing in a memory by a first processor, one or more credit management configuration programs received from the network controller, and establishing a first communication between at least said first processor and at least one second processor.

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Saint Etienne de Crossey, France

Christian Bernard