International Business Machines Corporation

Christian Bergeron

Raymond Lord

Mario Racicot

Luc Gilbert Guerin

Maryse Cournoyer

Pascale Gagnon

Paul Stephen Andry

Kamal Kumar Sikka

Jean Audet

Yang Liu

Richard D Langlois

Clement J Fortin

Steve E Whitehead

Pascal P Blais

Nathalie Meunier

Francois Arguin

An electronic package and a method of manufacture includes a substrate having an upper surface with a trench formed in a bridge region. First pads are arranged on the upper surface of the substrate, outside of the bridge region, and a bridge is positioned in the trench. A plurality of second pads are arranged on an upper surface of the bridge. A plurality of pillars are electrically coupled to the plurality of second pads. Two or more semiconductor chips are positioned in a side-by-side proximal arrangement overlaying the bridge and the substrate. A first semiconductor chip is joined to the bridge, then a second semiconductor chip is joined to the bridge, followed by attaching the chip-bridge assembly to the substrate with the bridge positioned within the substrate trench. Each of the two or more semiconductor chips have first electrical connections including bumps, and second electrical connections including third pads.

Mixed under bump metallurgy (UBM) interconnect bridge structure

A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.

High-density chip-to-chip interconnection with silicon bridge

A method for verifying the internal microstructure of interconnects in flip-chip applications includes providing a microelectronic assembly comprising the following: a substrate hosting an array of flip-chip attach pads and one or more process control pads; a flip chip having an array of solder bumps in contact with the array of flip-chip attach pads; and one or more representative solder bumps contacting the one or more process control pads. The representative solder bumps have a substantially similar or identical chemical composition as the array of solder bumps. A reflow cycle is then applied to the microelectronic assembly to melt and solidify the array of solder bumps on the flip-chip attach pads and melt and solidify the representative solder bumps on the process control pads. The surface texture of the representative solder bumps is then optically inspected to determine an internal microstructure of the array of solder bumps.

Technique for verifying the microstructure of lead-free interconnects in semiconductor assemblies

Circuit chips, such as known good die (KGD) chips, are removed from an assembly including a plurality of circuit chips attached to at least one chip carrier, or substrate. The substrate is held within a top plate with the circuit chips positioned within successive chip cavities within a bottom plate. Each chip cavity includes a load surface separated by a cascade effect pitch with respect to adjacent chip cavities. A cascade effect shear force is sequentially applied to the circuit chips to remove them from the substrate. The chips may be heated to a temperature facilitating shear within a temperature range at which solder connections are solid, and the chips further heated following disassembly to a temperature at which the solder is liquid to facilitate reforming the solder for subsequent attachment of the chip into an electronic device.

Apparatus and method for non-destructive, low stress removal of soldered electronic components

Apparatus and method for non-destructive, low stress removal of soldered

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Granby, Canada

Christian Bergeron