Thin Film Electronics Asa

Siemens Aktiengesellschaft

Ensurge Micropower Asa

Xerox Corporation

Christer Karlsson

Per Bröms

Hans Gude Gudesen

Johan Carlsson

Per Hamberg

Per-Erik Nordal

Jakob Nilsson

Olle Jonny Hagel

Geirr Ivarsson Leistad

Richard Hiram Womack

Göran Gustafsson

Staffan Björklid

Per Broms

Nicklas Ojakangas

Michael O Thompson

Mats Johansson

Thomas Hubauer

Per Sandström

Niklas Lövgren

Lars Sundell Torjussen

Nicklas Lövgren

Hamberg Per

Provided is a bot for a communication platform, wherein the bot is set up to read in an input data record, wherein the input data record includes a plurality of tickets or a plurality of numerical representations of tickets, listen in on at least one communication process between at least two persons on the communication platform, wherein the at least one communication process has at least one service case or at least one numerical representation of a service case, and generate an output data record, wherein the output data record has the input data record and the at least one communication process. A corresponding communication platform, a computer-implemented method, and a computer program product are also provided.

Bot for a communication platform

A battery management system having configurable batteries is disclosed. The battery management system generally includes (a) one or more cell control units, each cell control unit configured to control and/or balance a charge in a plurality of battery cells, and (b) a master controller in electrical communication with cell control unit(s). The cell control unit(s) as a whole include one or more switches, configured to be electrically connected to a first battery cell of a plurality of battery cells, and a resistor, a capacitor or an inductor electrically (i) connected to one switch and (ii) connected or connectable to a second battery cell. The master controller is configured to open or close each switch. The configurable battery generally includes a plurality of battery cells and switches configured to connect or disconnect the plurality of battery cells in a configurable or predetermined manner.

Circuitry and apparatuses for monitoring and controlling a battery and configurable batteries

A ferroelectric memory cell () and a memory device () comprising one or more such cells (). The ferroelectric memory cell comprises a stack () of layers arranged on a flexible substrate (). Said stack comprises an electrically active part () and a protective layer () for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer () and a top electrode layer () and at least one ferroelectric memory material layer () between said electrodes. The stack further comprises a buffer layer () arranged between the top electrode layer () and the protective layer (). The buffer layer () is adapted for at least partially absorbing a lateral dimensional change (&#x394;L) occurring in the protective layer () and thus preventing said dimensional change (&#x394;L) from being transferred to the electrically active part (), thereby reducing the risk of short circuit to occur between the electrodes.

Short circuit reduction in a ferroelectric memory cell comprising a stack of layers arranged on a flexible substrate

An electronic component () and an electronic device () comprising one or more such components (). The electronic component () comprises a stack () of layers arranged on a flexible substrate (). Said stack comprises an electrically active part () and a protective layer () for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer () and a top electrode layer () and at least one insulating or semi-insulating layer () between said electrodes. The stack further comprises a buffer layer (), arranged between the top electrode layer () and the protective layer (). The buffer layer () is adapted for at least partially absorbing a lateral dimensional change (&#x394;L) occurring in the protective layer () and thus preventing said dimensional change (&#x394;L) from being transferred to the electrically active part (), thereby reducing the risk of short circuit to occur between the electrodes.

Short circuit reduction in an electronic component comprising a stack of layers arranged on a flexible substrate

In a non-volatile electric memory system a memory unit and a read/write unit are provided as physically separate units. The memory unit is based on a memory material that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrodes and/or contacts are either provided in the memory unit or in the read/write unit and contacts are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected. The memory material of the memory unit can be polarized into two discernible polarization states.

Card-like memory unit with separate read/write unit

In a non-volatile electric memory system a card-like memory unit () and a read/write unit () are provided as physically separate units. The memory unit () is based on a memory material () that can be set to at least two distinct physical states by applying an electric field across the memory material. The read/write unit () comprises contact means () provided in a determined geometrical pattern enabling a definition of memory cells in memory unit () in an initial write operation, the memory cells being located in a geometrical pattern corresponding to that of the contact means (). Establishing a physical contact between the memory unit () and the read/write unit () closes an electrical circuit over an addressed memory cell such that read, write or erase operations can be effected. The memory material () of the memory unit () can be a ferroelectric or electret material that can be polarized into two discernible polarization states, or it can be a material with a resistive impedance characteristic such that a memory cell of the material can be set to a specific stable resistance value by the application of an electric field.

Data storage device

In a method for obviating the effect of disturb voltages in a data storage apparatus employing passive matrix addressing, an application of electric potentials for an addressing operation is according to a voltage pulse protocol. The data storage cells of the apparatus are provided in two or more electrically separated segments each constituting non-overlapping physical address subspaces of the data storage apparatus physical address space. A number of data storage cells in each segment are preset to the same polarization by an active voltage pulse with a specific polarization. In a first addressing operation one or more data storage cells are read by applying an active pulse with the same polarization to each data storage cell and recording the output charge response. On basis thereof the output data in subsequent second addressing operation are copied onto preset data storage cells in another segment of the data storage apparatus, this segment being selected on the basis of its previous addressing history.

Method for operating a data storage apparatus employing passive matrix addressing

In a method for reducing detrimental phenomena related to disturb voltages in a data storage apparatus employing passive matrix addressing, particularly a memory device or a sensor device, an application of electric potentials conforming to an addressing operation is generally controlled in a time-coordinated manner according to a voltage pulse protocol. In an addressing operation a data storage cell is set to a first polarization state by means of a first active voltage pulse and then, dependent on the voltage pulse protocol, a second voltage pulse which may be a second active voltage pulse of opposite polarity to that of the first voltage pulse, is applied and used for switching the data storage cell to a second polarization state. The addressed cell is thus set to a predetermined polarization state as specified by the addressing operation. The data storage cells of the apparatus are provided in two or more electrically separated segments such that each segment comprises a separate physical address space for the apparatus. In an addressing operation the data are directed to a segment that is selected based on information on prior and/or scheduled applications of active voltage pulses to the segments.

In a method for reading the memory cell in a passive matrix-addressable ferroelectric or electret memory array with memory cells in the form of ferroelectric or electret capacitors, sensing means connected to the bit line of memory cell is activated in order to initiate a charge measurement and a first charge value is registered, whereafter a switching voltage is applied to the memory cell and a second charge value is registered. A readout value is obtained by subtracting the first charge value from the second charge value. A sensing device for performing an embodiment of the method comprises a first amplifier stage with an integrator circuit and connected with a second amplifier stage (A) following the first amplifier stage and with an integrator circuit, and a sampling capacitor connected between an output of the first amplifier stage and an input of the second amplifier stage.

Read method and sensing device

In a method for operating a passive matrix-addressable ferroelectric or electret memory device, a voltage pulse protocol based on a 1/3 voltage selection rule is used in order to keep disturb voltages at minimum, the voltage pulse protocol comprising cycles for read and write/erase bases on time sequence of voltage pulses with defined parameters. The method comprises a refresh procedure wherein cells for refresh are selected and refresh requests processed by a memory device controller, the refresh requests are monitored and processed in regard of ongoing or scheduled memory operations, and refresh voltage pulses with defined parameters are applied to the memory cells selected for refresh, while simultaneously ensuring that non-selected memory cells are subjected to zero voltage or voltages which do not affect the polarization state of these cells.

Method for operating a passive matrix-addressable ferroelectric or electret memory device

A method of operating a passive matrix addressable ferroelectric device having a voltage pulse protocol with a pre-disturb and post-disturb cycle before and after a disturb generating operation cycle respectively in order to minimize the effect of disturb voltage on non-addressed memory cells, when such voltages are generated thereto in the operation cycle when It is applied for either a write or read operation.

Non-switching pre- and post- disturb compensational pulses

A passive matrix-addressable device may include individually addressable cells of a polarizable material. The cells store data in one of two polarization states in each cell, and the polarization states in the cells are written and read by addressing via electrodes which form word and bit lines. The cells are provided in or at the crossings between the word and bit lines and a voltage pulse protocol is used read and write data to cells. During reading, a word line is activated by applying voltage which relative to the potential on all crossing bit lines corresponds to the voltage Vand data stored in the cells connected to this active word line are determined by detecting the charge values of the cells.

Method for reading a passive matrix-addressable device and a device for performing the method

In methods for storing data in a non-volatile ferroelectric random access memory wherein destructive readout operations are followed by rewrite operations, identical copies of the data are stored in different memory locations that do not have any common word lines or alternative neither common word lines nor common bit lines. A first word line or a segment of a first word line is read in its entirety, said word line or said segment including at least a first copy of the identical copies of data. The data thus read are rewritten to the memory location and in addition transferred from the memory location in question to an appropriate cache location, whereafter subsequent memory locations either in the form of word lines or segments thereof are read, and data rewritten to the cache location. The operation is repeated until all identical copies of the data have been transferred to the cache storage. Subsequently bit errors are detected by comparing the identical copies in a memory control logic circuit, which also may be used for caching readout data copies or alternatively be connected with a separate cache memory. Corrected data are written back to the appropriate memory locations holding bit errors when the latter have been detected.

Growing community of inventors

Linköping, Sweden

Christer Karlsson