Telefonaktiebolaget Lm Ericsson (publ)

Infineon Technologies Ag

Csr Technology Inc.

Zoran Corporation

Fingerprint Cards Ab

Forsvarets Forskningsanstalt

Anacatum Design Ab

Fingerprint Cards Anacatum IP Ab

Christer Jansson

Bengt Erik Jonsson

Rolf Sundblad

Hans Thörnblom

Frank Robert Riedijk

Karl Lundahl

Mattias Palm

Wouter Brevet

Robert Hägglund

Emil Hjalmarson

Wenche Einerman

Ulf Ringh

In a pipelined Successive Approximation Register Analog to Digital Converter, SAR ADC, a Process, Temperature, and Voltage (PVT)-dependent bias voltage is generated and used to bias the inputs of comparators in at least the first SAR stage and residual amplifier (RA). This achieves a stable biasing and an operating point of the comparators and RA input stages that is independent of PVT variations, by tracking PVT variations in such a way that variations in MOS threshold voltage and drain-source voltage are counteracted. Additionally, a threshold common mode voltage is generated from the PVT-dependent voltage, which controls the amplification duration of the RAs such that the final RA output common mode voltage is substantially equal to the PVT-dependent voltage, which is used to bias the inputs of successive SAR stages. The threshold is set to account for logic delays in terminating the amplification based on the threshold comparison, to achieve the desired common mode amplifier output. The dependency on PVT of the threshold additionally cancels temperature variation from a differential stage transconductance of the RA. Further temperature stabilization is achieved by boosting the charge output by the RA to a capacitive load during part of the amplification.

PVT stabilization of pipelined SAR ADC

A method of determining a representation of a fingerprint pattern of a finger using a fingerprint sensor comprising a two-dimensional measuring arrangement including a plurality of measuring elements, each comprising a finger electrode spaced apart from the finger by a dielectric structure. For each measurement position, the method comprises the steps of: providing a first measuring element configuration with an elongated first measuring arrangement portion having a first principal direction of extension; and a first peripheral measuring arrangement portion; acquiring a first measurement value for the measurement position; providing a second measuring element configuration having an elongated second measuring arrangement portion having a second principal direction of extension; and a second peripheral measuring arrangement portion; and acquiring a second measurement value for the measurement position. The representation of the fingerprint pattern is determined based on the first measurement value and the second measurement value for each of the measurement positions.

Fingerprint sensing using measuring configurations with different principal directions of extensions

There is provided a capacitive fingerprint sensing device for sensing a fingerprint pattern of a finger, said capacitive fingerprint sensing device comprising: a protective top layer to be touched by said finger; a first metal layer comprising a two-dimensional array of sensing structures arranged underneath said top layer; a second metal layer, arranged underneath said first metal layer, comprising a plurality of conductive structures a dielectric layer arranged between the first and second metal layers to electrically insulate the first metal layer from the second metal layer, the dielectric layer comprising a low-k material; and readout circuitry arranged underneath said second metal layer and coupled to each of the electrically conductive sensing structures by means of via connections to receive a sensing signal indicative of a distance between said finger and said sensing structure. There is also provided a method for manufacturing such a device.

Fingerprint sensing device and method for manufacturing a fingerprint sensing device

A method of determining at least one calibration value for a redundant analog-to-digital-converter, ADC, is disclosed. For at least an i:th bit bL, the corresponding bit weight wis less than the sum of the bit weights W, j=0, 1, . . . , i&#x2212;1 corresponding to the bits b, j=0, 1, . . . , i&#x2212;1 with lesser significance than the bit bi. The method comprises sampling a first electrical value representative of the bit weight w; performing a first analog-to-digital, A/D, conversion using the bits b, j=0, 1, . . . , i&#x2212;1 with lesser significance than the bit bto obtain a first digital word of said bits b, j=0, 1, . . . , i&#x2212;1 with lesser significance than the bit brepresenting said first electrical value; and estimating the value of the bit weight Wexpressed in terms of the bit weights Wj. j=0, 1, . . . , i&#x2212;1 corresponding to the bits b, j=0, 1, . . . , i&#x2212;1 with lesser significance than the bit bbased at least on said first digital word, wherein the resulting estimated value of the bit weight wis one of the at least one calibration value. A control unit, a redundant ADC and a computer program are also disclosed.

ADC calibration

A comparator circuit () comprising a fully differential main amplifier unit (). The main amplifier unit () comprises a control port and is adapted to control a bias current of a first branch of the main amplifier unit () and/or a bias current of a second branch of the main amplifier unit () in response to one or more control voltages supplied to the control port of the main amplifier unit (). The comparator circuit () comprises circuitry () for balancing the voltages at the positive and negative input terminals () of the main amplifier unit () during a first clock phase of the comparator circuit (). Furthermore, the comparator circuit () comprises a switched-capacitor accumulator unit with a differential input. The switched-capacitor accumulator unit is operatively connected to the positive and negative output terminals () of the main amplifier unit () for sampling voltages at the positive and negative output terminals () of the main amplifier unit () during the first clock phase, and operatively connected to the control port of the main amplifier unit () for supplying said one or more control voltages.

Comparator circuit

A latched comparator circuit comprises an input amplification unit, a buffer unit, and a control unit. The input amplification unit comprises a first and a second input terminal for receiving a first and a second input voltage, respectively, of the latched comparator circuit. The input amplification unit further comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the input amplification unit. In addition, the input amplification unit comprises a reset terminal arranged to receive a reset signal for resetting the input amplification unit. The buffer unit is operatively connected to the first and the second output terminal of the input amplification unit. Furthermore, the buffer unit comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the buffer unit. The control unit is operatively connected to the input amplification unit and the buffer unit. The control unit is adapted to generate the reset signal based on the first and the second output voltage of the buffer unit and a clock signal and to generate an output signal of the latched comparator circuit based on the first and the second output voltage of the buffer unit. A method of operating the latched comparator circuit is also disclosed.

Latched comparator circuit

An arrangement is disclosed for offset compensation of a time-interleaved analog-to-digital converter, having a plurality of computing channels and being adapted to convert a signal from an analog domain to a digital domain. The arrangement comprises the time-interleaved analog-to-digital converter, an analog offset estimation and compensation unit adapted to estimate a mean offset for the plurality of computing channels, a digital offset estimation and compensation unit adapted to estimate a residual computing channel specific offset for each of the plurality of computing channels, and offset compensation means. The offset compensation means are adapted to perform offset compensation in the analog domain of each of the plurality of channels based on the estimated mean offset in the analog domain, and to perform offset compensation in the digital domain of each of the plurality of channels based on respective residual computing channel specific offset.

Methods of and arrangements for offset compensation of an analog-to-digital converter

A regulated voltage is generated at an output terminal of a voltage regulator circuit having at least one input terminal. A feedback signal is coupled from a first transistor coupled in parallel with a first resistor between the output terminal and the input terminal. The feedback signal is coupled to the input terminal to regulate the stability of the voltage regulator circuit. In a method of operation, the stability of a circuit is regulated by generating a feedback signal in the circuit to add a zero to a transfer function and raise an open loop phase curve of the circuit to result in a better power signal rejection ratio over a frequency range for the circuit.

Voltage regulator and associated methods

A latched comparator circuit. The latched comparator circuit comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the latched comparator circuit. Furthermore, the latched comparator circuit comprises a cross-coupled pair of transistors operatively connected between the first and the second output terminal for providing a positive feedback in the latched comparator circuit. In addition, the latched comparator circuit comprises a reset terminal for receiving a reset signal and reset circuitry arranged to balance the first and the second output voltage during a first phase of the reset signal and allow a voltage difference to develop between the first and the second output voltage during a second phase of the reset signal. Moreover, the latched comparator circuit comprises a load unit operatively connected to the cross-coupled pair of transistors and a bias circuit arranged to receive the reset signal and to bias the load unit such that a conductivity of the load unit is higher during the second phase of the reset signal than during the first phase of the reset signal, whereby said positive feedback is stronger during the second phase of the reset signal than during the first phase of the reset signal.

High-speed latched comparator circuit with variable positive feedback

A clock-signal generating unit for generating an output clock signal with a controlled duty cycle based on an input clock signal. The clock-signal generating unit comprises one or more delay lines arranged to generate a plurality of mutually delayed output signals at different positions within the delay line based on the input clock signal. A control unit is arranged to detect a position within one of the delay lines, the output signal of which has a delay, with respect to the input clock signal, that is essentially equal to one period of the input clock signal, and generate an output signal that indicates the detected position. A selection unit is arranged to generate a delayed clock signal that has a delay, with respect to a signal associated with the input clock signal, that is essentially equal to a period of the clock signal multiplied with said duty cycle based on output signals from one of the delay lines and the output signal of the control unit. The clock-signal generating unit comprises circuitry for generating the output clock signal based on the signal associated with the input clock signal and the delayed clock signal. A corresponding method of generating an output clock signal with a controlled duty cycle based on an input clock signal is also disclosed.

Clock-signal generator

An A/D converter stage including an A/D sub-converter connected to a D/A sub-converter () is calibrated by a method that inserts a calibration test sequence into the D/A sub-converter. This is accomplished by forcing (SW) the comparators (COMP-COMP) of the A/D sub-converter to generate and insert the sequence into the D/A sub-converter.

A/D converter calibration test sequence insertion

An A/D converter includes at least one comparator array (COMP&#x2013;COMP) for flash A/D conversion of an analog signal. Means (CCU, SW&#x2013;SW) provide, for each comparator in the array, a common reference signal to both comparator input terminals. Means (CCU, DAC&#x2013;DAC) force each compara-tor in the array into the same logical output state. Finally, means (CCU, DAC&#x2013;DAC) adjust the comparator trip-point for each comparator by a ramp signal until the logical output state is inverted.

Comparator offset calibration for A/D converters

A D/A converter range calibration system in an A/D converter structure including a set of comparators with associated calibrating D/A converters includes means (RCC) for determining the offset error range for the entire set of comparators and means (R-DAC) for adjusting the dynamic range of each calibrating D/A converter to this offset error range.

A/D converter calibration

A comparator for an analog-to-digital converter comprises an input stage (in , in , M , M ) for receiving an input signal; a bipolar latch stage (Q , Q ; Q , Q ) coupled to the input stage for performing a latch decision based on the input signal; means for amplifying the latch output (V , V ) to a level suitable for CMOS circuitry; and an output (out , out ). The means for amplifying includes at least one tapping transistor (Q , Q ) coupled to the latch stage for, depending on the latch decision, tapping a collector current (I ; I ) from the latch stage, while leaving the latch decision thereof unaffected, such that a current gain (&bgr;) of the latch stage can be used to amplify a latch bias current (I , I ) of the latch stage to thereby provide for the amplification.

Comparator circuit and method of operating a comparator circuit

An A/D converter stage including an A/D sub-converter connected to a D/A sub-converter provides dynamic element matching. This is accomplished by forcing comparators of the A/D sub-converter to generate a scrambled thermometer code.

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Linköping, Sweden

Christer Jansson