Soitec

Centre National De La Recherche Scientifique

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Universite Claude Bernard – Lyon1

Soitec Belgium

Christelle Veytizou

Oleg Kononchuk

Didier Landru

Ionut Radu

Frédéric Allibert

Eric Guiot

Isabelle Bertrand

Fabrice Gritti

Marcel Broekaart

Emmanuel Augendre

Christophe Figuet

Patrick Reynaud

Stefan Degroote

Joff Derluyn

Frédéric Gaillard

Emmanuel Rolland

Luciana Capello

Damien Radisson

Thomas Lorne

Kassam Alassaad

Gabriel Ferro

Véronique Souliere

Taguhi Yeghoyan

YoungPil Kim

A semiconductor structure for radio frequency applications includes a support substrate made of silicon and comprising a mesoporous layer, a dielectric layer arranged on the mesoporous layer and a superficial layer arranged on the dielectric layer. The mesoporous layer comprises hollow pores, the internal walls of which are mainly lined with oxide. The mesoporous layer has a thickness between 3 and 40 microns and a resistivity greater than 20 kohm·cm over its entire thickness. The support substrate has a resistivity between 0.5 and 4 ohm·cm. The invention also relates to a method for producing such a semiconductor structure.

Semiconductor structure comprising a buried porous layer for RF applications

A hybrid structure for a surface acoustic wave device comprises a working layer of piezoelectric material assembled with a support substrate having a lower coefficient of thermal expansion than that of the working layer, and an intermediate layer located between the working layer and the support substrate. The intermediate layer is a sintered composite layer formed from powders of at least a first material and a second material different from the first.

Hybrid structure for surface acoustic wave device and associated production method

A substrate for radiofrequency microelectronic devices comprises a carrier substrate made of a semi-conductor, a sintered composite layer disposed on the carrier substrate and formed from powders of at least a first dielectric material and a second dielectric different from the first material, the sintered composite layer having a thickness larger than 5 microns and a thermal expansion coefficient that is matched with that of the carrier substrate to plus or minus 30%.

Substrate for radiofrequency applications and associated manufacturing method

A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm&#xb7;cm and a thickness greater than 5 microns positioned on the first insulating layer.

Support for a semiconductor structure

A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm&#xb7;cm.

Carrier for a semiconductor structure

A process for avoiding formation of an Si&#x2014;SiO&#x2014;Henvironment during a dissolution treatment of a semiconductor-on-insulator structure that includes a carrier substrate, an oxide layer, a thin layer of a semiconductor material and a peripheral ring in which the oxide layer is exposed. This process includes encapsulating at least the exposed oxide layer of the peripheral ring with semiconductor material by performing a creep thermal treatment; and performing an oxide dissolution treatment to reduce part of the thickness of the oxide layer. In this process, the semiconductor material that encapsulates the oxide layer has a thickness before the oxide dissolution that is at least twice that of the oxide that is to be dissolved, thus avoiding formation of an Si&#x2014;SiO&#x2014;Henvironment on the peripheral ring where the oxide layer would otherwise be exposed.

Process to dissolve the oxide layer in the peripheral ring of a structure of semiconductor-on-insulator type

A process for treating a semiconductor-on-insulator type structure that includes, successively, a support substrate, an oxide layer and a thin semiconductor layer. The process includes formation of a silicon nitride or silicon oxynitride mask on the thin semiconductor layer to define exposed areas at the surface of the layer which are not covered by the mask, and which are arranged in a desired pattern; and application of a heat treatment in a neutral or controlled reducing atmosphere and under controlled conditions of temperature and time to induce at least a portion of the oxygen of the oxide layer to diffuse through the thin semiconductor layer, thereby resulting in the controlled reduction in the oxide thickness in the areas of the oxide layer corresponding to the desired pattern. The mask is formed so as to be at least partially buried in the thickness of the thin semiconductor layer.

Process for locally dissolving the oxide layer in a semiconductor-on-insulator type structure

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Bernin, France

Christelle Veytizou