Koninklijke Philips Corporation N.v.

Vlsi Technology, Inc.

Philips Semiconductors Inc.

Christelle Faucon

Christian Ponte

Olivier Giaume

Philippe Alves

Beatrice Brochier

Jean-Francois Duboc

Jean Francois Duboc

Pierre Yves Challier

Method of testing an integrated circuit having a flexible timing control

A system for transferring data in a single clock cycle between a digital signal processor (DSP) and an external memory unit and method of same. The system includes a data transfer element coupled between the external memory unit and the DSP, where the data transfer element is adapted to transfer the data between the external memory unit and the DSP in a single clock cycle. In one embodiment, the data transfer element is a coprocessor including a plurality of latch devices coupled to buses between the DSP and the memory unit. A first set of data are transferred from a first memory unit (e.g., from either the DSP internal memory unit or the external memory unit, depending on the direction of the data transfer) into the coprocessor during a first clock cycle and out of the coprocessor to a second memory unit in a second clock cycle occurring immediately after the first clock cycle. Data subsequent to the first set are similarly transferred during each clock cycle occurring immediately thereafter, so that data are transferred out of the first memory unit and into the second memory unit each clock cycle.

System for priming a latch between two memories and transferring data via the latch in successive clock cycle thereafter

An interface system for testing and verifying the design of an ASIC at different levels of abstraction, wherein the ASIC includes a logic entity and a processor entity. The system of the present invention is embodied as software which executes within a computer system. The software, when executed by the computer system, causes the computer system to implement a model of the ASIC, a simulator, and a test interface. The model of the ASIC is embodied in HDL (Hardware Description Language) and includes a logic entity and a processor entity. The simulator is adapted to test the model. The test interface interfaces the model with the simulator. The test interface includes a simulator portion and a model portion. The simulator portion is coupled to the simulator. The model portion is embodied in HDL and is coupled to both the logic entity and the processor entity. The model portion and the simulator portion are coupled to exchange information. The model portion is operable to obtain register status information of the processor entity and provide the register status information to the simulator via the simulator portion such that the register status is observable by the simulator as the model is simulated at different of levels of abstraction.

HDL simulation interface for testing and verifying an ASIC model

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Plascassier, France

Christelle Faucon