Commissariat a L'energie Atomique Et Aux Energies Alternatives

Commissariat a L'energie Atomique

Stmicroelectronics (Crolles 2) Sas

Commissariat a L'energie Atmoique

Christelle Charpin-Nicolle

Eric Jalaguier

Florian Pebay-Peyroula

Sophie Bernasconi

Aomar Halimaoui

Nicolas Guillaume

Anthony De Luca

Rémy Gassilloud

Laurent Grenouillet

Sébastien Kerdiles

Gabriele Navarro

Ludovic Poupinet

Luca Perniola

Jean Coignus

Remy Gassilloud

Mathieu Bernard

Jean-Yves Robic

Serge Blonkowski

Thomas Magis

Alain Persico

Boubacar Traore

Béatrice Biasse

Terry Francois

This method comprises the following steps:

Method for manufacturing resistive memory cells

A method for manufacturing a microelectronic device including resistive memory points, a first portion of the memory points forming a physical unclonable function, the memory points of the first portion forming a PUF zone, a second portion of the memory points providing a memory function, the memory points of the second forming a memory zone, the method including providing a support including a first electrode layer and an active oxide resistive memory layer; etching the active oxide resistive memory layer in the PUF zone; etching the active oxide resistive memory layer in the memory zone, the etching in the memory zone producing a dispersion of roughness of the oxide layer less than the dispersion of roughness produced by the etching in the PUF zone; depositing a second electrode layer; etching the second electrode layer, the active oxide layer and the first electrode layer to define the memory points.

Method for manufacturing a microelectronic device comprising a plurality of resistive memory points configured to form a physical unclonable function and said device

A microelectronic device and method for manufacturing a microelectronic device comprising a plurality of resistive memories, a part of these resistive memories, called PUF memories, forming a PUF, the rest of these resistive memories being known as storage memories. The manufacturing process comprising forming a dielectric layer having on at least one contact surface in contact with an electrode a surface roughness of said surface greater than that of the same dielectric layer of the storage memories.

Method for manufacturing a microelectronic device integrating a physical unclonable function provided by resistive memories, and said device

An OxRAM oxide based resistive random access memory cell includes a first electrode; a layer M1Oss of a sub-stoichiometric oxide of a first metal; a layer M2N of a nitride of a second metal M2; a layer M3M4O of a ternary alloy of a third metal M3, a fourth metal M4 and oxygen O, or M3M4NO of a quaternary alloy of the third metal M3, the fourth metal M4, nitrogen N and oxygen O and a second electrode. The standard free enthalpy of formation of the ternary alloy M3M4O, noted &#x394;G(M3M4O), or of the quaternary alloy M3M4NO, noted &#x394;G(M3M4NO), is strictly less than the standard free enthalpy of formation of the sub-stoichiometric oxide M1Oss of the first metal M1, noted &#x394;G(M1Oss), itself less than or equal to the standard free enthalpy of formation of any ternary oxynitride M2NO of the second metal M2, noted &#x394;G(M2NO):&#x394;(34O)&#x3c;&#x394;(1)&#x2264;&#x394;(2NO)or &#x394;(34NO)&#x3c;&#x394;(1)&#x2264;&#x394;(2NO).

OxRAM oxide based resistive random access memory cell and associated manufacturing method

A method for securing an integrated circuit upon making it includes the steps of delimiting said integrated circuit into a first so-called standard zone and into a second so-called security zone, and randomly misaligning in said security zone between a lower level of interconnection holes and an upper level of interconnection holes generating the formation of an interconnection structure having a random distribution of electrical contact and non-contact points. Also described is a secured integrated circuit obtainable using such a method.

Method for securing an integrated circuit upon making it

A method of fabrication of a ferroelectric memory including a first electrode, a second electrode and a layer of active material made of hafnium dioxide HfOpositioned between the first electrode and the second electrode, where the method includes depositing a first electrode layer; depositing the layer of active material; doping the layer of active material; depositing a second electrode layer; wherein the method includes sub-microsecond laser annealing of the layer of doped active material.

Method for fabricating a ferroelectric memory and method for co-fabrication of a ferroelectric memory and of a resistive memory

The present invention relates to a method for producing a via through a base layer of a microelectronic device, the method including formation of a hole leading to at least one first face of the base layer and filling the hole by at least one first filling material. The method also includes at least partially removing the at least one first filling material over a depth from the first face of the base layer, the depth being strictly less than a thickness dimension of the hole, so as to produce a hollow portion. Further, method includes a second step of at least partially filling the hollow portion by at least one second filling material.

Method for manufacturing a pass-through device

A method for manufacturing a resistive random access memory includes depositing a layer made of an active material of variable electrical resistance on a substrate containing a first electrode, forming a lower electrode; depositing an electrically conductive layer on the active material layer; etching the electrically conductive layer so as to delimit a second electrode, forming an upper electrode, facing the lower electrode; exposing at least one flank of the upper electrode to an ion beam inclined with respect to the normal to the substrate by an angle (&#x3b1;) comprised between 20&#xb0; and 65&#xb0;, so as to implant the ions in a portion of the active material layer adjacent to the flank and located under the upper electrode, the ion implantation conditions being chosen so as to create defects in the structure of the active material and to obtain an average implantation width comprised between 5 nm and 10 nm.

Method for manufacturing a resistive memory

The present invention relates to a memory device comprising a first electrode (), a second electrode () and an active portion that can change conductive state, positioned between a first face of the first electrode () and a first face of the second electrode (). The first electrode () comprises an upper portion forming the first face of the first electrode (). At least one out of the upper portion and the active portion that can change conductive state comprises a porous layer ().

Method of manufacturing a memory device

A method for manufacturing resistive random access memories, each resistive random access memory including first and second electrodes separated by a layer of active material, the method including producing connector elements with a step Cp along a first direction, each connector element having a width Cb along the first direction; producing a plurality of first electrodes with a step Ep along the first direction, each first electrode having a first end surface and a second end surface, the second end surface having a width Eb along the first direction and an area greater than the area of the first end surface; wherein:

Method for manufacturing a resistive random access memory; having reduced variability of electrical characteristics

A method for manufacturing a memory cell includes forming a stack of layers comprising a first electrode and a dielectric layer, and forming a second electrode. Forming the second electrode includes depositing the second electrode on the dielectric layer, and defining the contour of the second electrode in such a way that the second electrode forms a protruding element above the dielectric layer having inclined flanks, the angle between the flanks of the second electrode forming an acute angle with the plane wherein the dielectric layer mainly extends.

Method for producing a resistive memory cell

A memory device, containing a first electrode, a second electrode and an oxide layer arranged between the first electrode and the second electrode, is produced. The oxide layer has a first zone and a second zone, with the first zone surrounding or being located on either side of the second zone, with the minimum distance dseparating the two electrodes on the second zone of the oxide layer being less than the minimum distance dseparating the two electrodes on the first zone of the oxide layer.

Memory device

A method of manufacturing a spacer for an electronic memory including a substrate; a first gate structure; a stack including a plurality of layers whereof at least one of the layers is able to store electric charges, the method including depositing a spacer material layer, at least on the area covered by the stack; ion beam machining the spacer material layer, the ion beam machining being carried out with controlled stopping so as to preserve a residual portion of the thickness of the spacer material layer covering the stack; plasma etching the residual portion of the thickness of the spacer material layer.

Method of manufacturing a spacer for dual gate electronic memory cell and associated electronic memory cell

A method of manufacturing a double-gate electronic memory cell is presented. The cell includes a substrate; a first gate structure, with the first gate structure having a lateral flank; a stack including several layers and of which a layer is able to store electrical charges, the stack covering the lateral flank of the first gate structure and a portion of the substrate; and a second gate structure. The second gate structure includes a first portion formed from a first gate material; a second portion formed from a second gate material, with the first gate material able to be etched selectively in relation to the second gate material and with the second gate material able to be etched selectively in relation to the first gate material; a first zone of silicidation extending over the first portion of the second gate structure; and a second zone of silicidation extending over the second portion of the second gate structure.

Method for manufacturing a double-gate electronic memory cell and associated memory cell

A method of making a non-volatile double-gate memory cell. A gate of the control transistor is formed with a relief on a substrate. A control gate of the memory transistor is formed with a layer of a semiconductor material covering relief. The method includes chemical mechanical polishing (CMP) so as to strip, above the relief another layer and part of the layer of a semiconductor material; stripping of the remaining other layer on both sides of the relief, etching of the layer of a semiconductor material so as to strip this material above the relief and to leave only a pattern on at least one sidewall of the relief.

Growing community of inventors

Fontanil-Cornillon, France

Christelle Charpin-Nicolle