Irvine Sensors Corporation

Microsensors Corp.

Christ H Saunders

Ying Wen Hsu

John C Carson

David E Ludwig

Robert Edward DeCaro

John William Reeds, Iii

Raphael R Some

Kirk Su

Dale Maeding

John J Stuart

A transducer interface circuit ( ) for use with a capacitive sensor ( ). The interface circuit ( ), provided on application specific IC, includes numerous trims and adjustments that permit it to operate with a differential, balanced-pair sensors ( A) or a singled-ended sensor ( ). In particular, the circuit ( ) provides a capacitive adjustment section ( ) and a capacitive trans-impedance amplifier section ( ) that are configured with capacitor adjustment controls ( ) and gain adjustment controls ( ) that, along with other controls, are provided as control registers. The capacitive trans-impedance amplifier section ( ) periodically reverses the voltages across the sensor ( ), and the capacitive adjustment section ( ), after blanking a feedback capacitance (CF) that is used to integrate excess charge caused by a difference in capacitance. A low pass filter section provides bandwidth adjustment without requiring any external components. An output buffer section ( ) includes further trim controls for gain and offset, is also governed by an offset selection bit SOFF that adjusts the output range to be optimally suited for the balanced-pair sensors ( A) or a singled-ended sensor ( B).

Highly configurable capacitive transducer interface circuit

A neural processing module is disclosed which combines a weighted synapse array that performs &ldquo;primitive arithmetic&rdquo; (products and sums) in parallel with a weight change architecture and a data input architecture that collectively maximize the use of the weighted synapse array by providing it with signal permutations as frequently as possible. The neural processing module is used independently, or in combination with other modules in a planar or stacked arrangement.

Neural processing module with input architectures that make maximal use of a weighted synapse array

A micro-gyro device is disclosed combining an element which oscillates around the drive axis and an element which rocks around the output axis, so arranged that Coriolis force is transmitted from one element of the other without any substantial transfer of motion of either element to the other in its own direction of motion. In other words, the masses of the two elements operate independently of one another, providing improved performance, and individual adjustability to compensate for any manufacturing imprecision. The presently-preferred device combines an outer ring which oscillates around the drive axis with an inner disk which rocks around the output axis, whenever external rotating motion occurs about the rate axis.

Multi-element micro gyro

Circuitry for sensing a relatively large number of events, and outputting to processing circuitry only those events which have two characteristics: (1) a magnitude above a preselected threshold level, and (2) a rate of change greater than a preselected background rate of change. Logic circuitry is used to assign any event which has the desired characteristics to an available output channel. Subtracter circuitry causes the background to be subtracted from the sensing input, in order to limit the output to non-background events.

Sensing and selecting observed events for signal processing

An electronic package is disclosed in which a plurality of stacked 'same function' IC chips are designed to be used in lieu of a single IC chip, and to fit into a host computer system, in such a way that the system is 'unaware' that substitution has been made. Memory packages are of primary interest, but other packages are also feasible, such as packages of FPGA chips. In order to 'translate' signals between the host system and the stacked IC chips, it is necessary to include suitable interface circuitry between the host system and the stacked chips. Specific examples are disclosed of a 4 MEG SRAM package containing 4 stacked IC chips each supplying a 1 MEG memory, and of 64 MEG DRAM packages containing 4 stacked IC chips each supplying a 16 MEG memory. The interface circuitry can be provided by a single special purpose IC chip included in the stack, referred to as a VIC chip, which chip provides both buffering and decoding circuitry. Additionally, the VIC chip should provide power supply buffering. And, if it has sufficient real estate, such performance enhancing functions as error correction, memory cache, and synchronized memory may be included in the VIC chip circuitry.

Stack of IC chips in lieu of single IC chip

A wireless infrared pulse-transmitting system for communication with electronic components. The receiver for such a system has radically reduced current (and power) values, which permit a battery-powered receiver to remain on while awaiting transmitter signals. Use of several mosfet transistors operating in the subthreshold region minimizes power. Bandwidth requirements are met, in spite of the low power operation. In order to eliminate amplifier saturation, with the accompanying problem of recovery time which slows the transmission process, clamping circuitry is used to cause instantaneous shunting of signals when a predetermined signal level is reached.

Growing community of inventors

Laguna Niguel, CA, United States of America

Christ H Saunders