University of Dayton

Chris Yakopcic

Tarek M Taha

Md Raqibul Hasan

Raqibul Hasan

Md Shahanur Alam

Shuo Zhang

A spiking neural network (SNN) system is disclosed having spiking neurons associated with clause values associated with a satisfiability (SAT) problem. Each spiking neuron generates a voltage spike when on input voltage applied to each spiking neuron is increased above a spiking voltage threshold. The input voltage that is increased above the spiking voltage threshold is indicative that the corresponding clause value is satisfied. A controller applies the clause grid that includes clause values to a literal grid that includes literal values. The controller generates the input voltage that is applied to each spiking neuron based on each corresponding clause value associated with each spiking neuron that is applied to the literal values. The controller determines that each clause value is satisfied when the corresponding spiking neuron generates the voltage spike and that each clause value is unsatisfied when the corresponding spiking neuron fails to generate the voltage spike.

Satisfiability problem solver implemented on spiking neural network embedded systems

An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.

Analog neuromorphic circuits for dot-product operation implementing resistive memories

A modulation classification and demodulation system is disclosed having a modulation classifier and a demodulator to classify modulations and then demodulate received signals that deviate during propagation from noise. The modulation classifier classifies each type of modulation for each signal transmitted to the receiver in a sequenced modulation signal into a corresponding modulation class based on a modulation classifier neural network that identifies each type of modulation. The sequenced modulation signal that is received by the modulation classifier is deviated from when initially transmitted by the transmitter based on noise that impacts the sequenced modulation signal as the sequenced modulation signal propagates from the transmitter. The demodulator demodulates the receives signal by decoding each symbol included in the received signal based on the determined modulation class of the received signal. The determined modulation class identifies each symbol in the determined modulation class to decode when deviated by noise.

Modulation classification and demodulation system with a neural network

An analog neuromorphic circuit is disclosed having a first and a second memristor crossbar configuration implemented into an autoencoder. The first memristor crossbar configuration includes resistive memories that provide resistance values to each corresponding input voltage applied to the first memristor crossbar configuration to generate first output voltages that are compressed from the input voltages. The second memristor crossbar includes resistive memories that provide resistance values to each corresponding first output voltage applied to the second memristor crossbar configuration to generate second output voltages that are decompressed from the first output voltages. A controller compares the second output voltages to the input voltages to determine if the second output voltages are within a threshold of the input voltages. The controller generates an alert when the second output voltages exceed the threshold from the input voltages thereby indicating that input data associated with the input voltages has not been previously identified.

Unsupervised learning of memristor crossbar neuromorphic processing systems

An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

Analog neuromorphic circuit implemented using resistive memories

An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to an input voltage signal as the input voltage signal propagates through the resistive memories generating a first output voltage signal and to provide a resistance to a first error signal that propagates through the resistive memories generating a second output voltage signal. A comparator generates the first error signal that is representative of a difference between the first output voltage signal and the desired output signal and generates the first error signal so that the first error signal propagates back through the plurality of resistive memories. A resistance adjuster adjusts a resistance value associated with each resistive memory based on the first error signal and the second output voltage signal to decrease the difference between the first output voltage signal and the desired output signal.

On-chip training of memristor crossbar neuromorphic processing systems

A crossbar circuit determines a match of N bits of data to at least one of M target words simultaneously. The circuit comprises N inputs (one per data bit) and M outputs (one per target word). For each of the M target words, the circuit comprises N&#x2212;1 biased bits, where each biased bit includes a first data memristor coupled to a corresponding one of the N inputs; a second data memristor coupled to the corresponding one of the N inputs, where the corresponding one of the N inputs is inverted before reaching the second data memristor; and two biasing memristors. Further, the circuit comprises a general bit comprising a first data memristor coupled to the input that does not correspond to any of the biased bits; and a second data memristor coupled to the input that does not correspond to any of the biased bits and is inverted.

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Dayton, OH, United States of America

Chris Yakopcic