Altera Corporation

Chris Wysocki

Vaughn Betz

Andy Louie Lee

David Lewis

Christopher F Lane

Paul Leventis

Alexander Marquardt

Bruce B Pedersen

Henry Kim

Vikram Santurkar

Michael David Hutton

Gregg William Baeckler

Jinyong Yuan

Zahir Parpia

Pouyan Djahani

Richard G Cliff

Srinivas T Reddy

Cameron R McClintock

Brian D Johnson

Lyndon Francis Carvalho

Derek So

Tim Michael Vanderhoek

Adrian Ludwin

Jungmoo Oh

Programmable integrated circuits with configurable logic circuitry and routing resources are provided. Portions of the routing resources on a programmable integrated circuit may be used in implementing a desired user-specified custom logic function, whereas other portions of the routing resources on the programmable integrated circuit may be unused. The unused routing resources may include adjacent pairs of routing paths. These paths may be coupled to control circuitry configured to drive the routing paths to desired voltage levels to provide an optimal amount of decoupling capacitance. In one suitable arrangement, two adjacent routing paths may both be driven to a positive power supply voltage level. In another suitable arrangement, the two adjacent routing paths may be driven to the positive power supply voltage level and a ground power supply voltage level, respectively.

Programmable integrated circuits with decoupling capacitor circuitry

A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers

A method for designing a system on a target device includes performing delay annotation where a first delay associated with a first aspect of the system is determined by a first software thread and a second delay associated with a second aspect of the system is determined by a second software thread and the first and second software threads operate in parallel. Ensuring independence between each aspect of the system will facilitate efficient parallelism (i.e. minimal synchronization) while still maintaining serial equivalency.

Method and apparatus for performing delay annotation

A method for designing a system on a field programmable gate array (FPGA) includes routing one or more booster wires alongside an interconnect to reduce a delay of a signal being transmitted on the interconnect. According to one aspect of the present invention, the routing of the one or more booster wires is performed in response to determining that a timing requirement of the system has not been met.

Method and apparatus for implementing cross-talk based booster wires in a system on a field programmable gate array

A method for designing a system on a target device includes identifying components and routing connections impacted by incremental design changes made to a system design. New information is computed to annotate delays for the components and routing connections identified. Delays previously computed for components and routing connections are utilized to annotate delays for components and routing connections that have not been impacted by the changes made to the system design.

Method and apparatus for performing incremental delay annotation

A method for determining a delay through a lookup table (LUT) in a logic array block (LAB) of a field programmable gate array (FPGA) for a signal includes identifying paths through the LUT that are taken for the signal. Delays are computed for the signal only on the paths identified.

Method and apparatus for performing lutmask based delay modeling

A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

An embodiment of this invention pertains to a versatile and flexible logic element and logic array block ('LAB'). Each logic element includes a programmable combinational logic function block such as a lookup table ('LUT') and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an &#x201c;add-or-subtract control signal&#x201d; that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

Versatile logic element and logic array block

An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks ('LABs'), within a programmable logic device ('PLD'). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides.

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Toronto, Canada

Chris Wysocki