Intel Corporation

Chris Wilkerson

Shih-Lien L Lu

James W Tschanz

Ming Lei Zhang

Edward Thomas Grochowski

Greg F Taylor

Randy J Aksamit

Murali M Annavaram

Alaa R Alameldeen

Jared Warner Stark, Iv

Nam Sung Kim

Keith A Bowman

Renju Thomas

Vivek K De

Muhammad M Khellah

Dinesh Somasekhar

Tanay Karnik

Wei Wu

Herbert H Hum

Zeshan A Chishti

Janice C Lee

Tingting Sha

James Tachanz

Tanay Karnlk

Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.

Apparatus and method to reduce memory power consumption by inverting data

A method and apparatus for handling low power and high performance loads is herein described. Software, such as a compiler, is utilized to identify producer loads, consumer reuse loads, and consumer forwarded loads. Based on the identification by software, hardware is able to direct performance of the load directly to a load value buffer, a store buffer, or a data cache. As a result, accesses to cache are reduced, through direct loading from load and store buffers, without sacrificing load performance.

Compiler assisted low power and high performance load handling based on load types

Memory data inversion for reducing power consumption

Data inversion based approaches for reducing memory power consumption

Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.

Sequential circuit with error detection

A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits.

Performing multi-bit error correction on a cache line

Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Method and apparatus for late timing transition detection

Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value.

Delay fault detection using latch with error sampling

Associated with an instruction in a program is a computation history. The computation history represents all objects that affect the result of the instruction, such objects including (but not limited to) registers, memory locations, static values, and instruction program counters. The computation history may be used to make a prediction about a property of the instruction.

Using computation histories to make predictions

Methods and systems to facilitate an efficient circuit for detecting internal timing errors for integrated devices, including a hierarchy of reporting the detection of the timing error from a circuit level to a functional unit block (FUB) level up to a global detection, and a reorder buffer (ROB) for storing a result for timing error recovery until the timing can be verified to be error free.

Method, system and apparatus for detecting and recovering from timing errors

Growing community of inventors

Portland, OR, United States of America

Chris Wilkerson