Hughes Electronics Corporation

Chris Weaver

Daniel R Wendling

Wayne McNinch

A data transfer device for transferring data between a plurality of digital signal processors in a system utilizing time division multiple access techniques. The data transfer device includes a system controller coupled to a bus network, a plurality of dual port random access memories, and a direct memory access controller. Each dual port random access memory device includes a first input/output port coupled to one of the plurality of digital signal processors, and a second input/output port coupled to the bus network. Each of the plurality of digital signal processors can access the dual port random access memory device coupled thereto during a first predefined time within a TDMA cycle. During a second predefined time period within the same TDMA cycle, the direct memory access controller, under control of the system controller, transfers data directly between the dual port random access memory devices. During a third predefined time period within the same TDMA cycle, the system controller can access the dual port random access memory devices coupled thereto.

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Takoma Park, MD, United States of America

Chris Weaver