Other

Super Talent Electronics, Inc.

Sartre Satire LLC

Hangzhou Dianzi University

Chris Tsu

Andy P Annadurai

Feng Han

Charles Chung Lee

Jianjun Luo

Mohammed Abdul Rahman

David Q Chow

Hon-Ming Li

Ming-Shiang Shen

Shi Wang

Lingyan Fan

Hong-Ming Li

A card reader controller engine includes an interface controller responsive to information. The engine is coupled to the interface controller and is configured to compress the information before the information is to be stored in a memory card. A master interface is coupled to the engine and is further responsive to the compressed information for storage in the memory card.

Distributed cryptography system

Method and apparatus for processing data packets within a communication system such as a synchronous optical network (SONET) detect an invalid byte and drop and shift bytes of data to address an invalid byte. A method according to one embodiment of the present invention, includes receiving a first data packet in the communication system. Thereafter, it is determined whether this packet ends with both a valid byte and an invalid byte of data. If both the valid and invalid bytes are present, the invalid byte is dropped and a valid byte from a succeeding data packet is concatenated with the valid byte of the first data packet, and byte shifting occurs in the succeeding data packet. Byte shifting continues until a second packet ending with an invalid byte is encountered. Skipping a clock cycle at the end of the second packet with the invalid byte results in packets with only valid data.

Circuit and method for processing communication packets and valid data bytes

A flash memory system includes flash memory organized into a plurality of blocks of pages for storage of information, a page including data and spare, the blocks being identifiable, within the flash memory, by a physical address. The system further has a flash controller for communicating with a host and the flash memory and includes volatile memory for storing a source-shadow table of logical addresses identifying blocks addressable by the physical addresses. The source-shadow table has an address mapping table and a property value table. The property value table is used to store property values, each of which is associated with a block of a predetermined group of blocks and is indicative of the number of times a block has been written since the last erase operation performed thereon. The property values correspond to the logical addresses of the address mapping table, wherein a block having been written no more than two times is re-written to different areas of the flash memory without requiring an erase operation.

Source and shadow wear-leveling method and apparatus

A flash memory system includes a multi level cell (MLC) flash memory organized into blocks and having pages of information, which has data and spare. The MLC flash memory includes at least a temporary area to store at least a portion of a page of information during a partial write operation. The MLC flash memory stores a page of information into a block identified by a target physical address. The flash memory system further includes a flash card micro-controller causes communication between a host flash card controller and the MLC flash memory and includes a buffer memory configured to store a portion of a page of information, where the micro-controller writes the at least a portion of a page of information to the temporary area and later copies the written at least a portion of a page of information into the block identified by a target physical address.

Partial-write-collector algorithm for multi level cell (MLC) flash

A method and circuitry for detecting a pattern in received data such as the A1A2 boundary in a SONET frame after deserialization. Two consecutive pluralities of bytes of incoming data are stored and compared with the A1 and A2 values (or bit shifted versions of the A1 and A2 values) until the boundary is detected. The data are then bit shifted so that every byte on the bus is either A2 or A1. A new aligned data bus is then formed such that the last A1 bit occurs on the data bus for a given clock cycle and the first A2 bit occurs on the data bus during the next clock cycle.

Method and circuit for processing data in communication networks

A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.

Page and block management algorithm for NAND flash

Method and circuitry for de-skewing data in data communication networks such as a SONET. The data is sent from a system chip to a framer chip where the data is de-skewed. To detect data skew, the system chip sends a training sequence to the framer chip. The information bits sent to the framer chip are searched in order to detect the training sequence. The training sequences contain clear transition patterns at which all 16 bits of the transmit data and the TCTL signal line are inverted. If any bit does not invert, this bit must be a skewed bit. Based on the data one clock cycle before and one clock cycle after this transition, the skewed bit can be corrected back. After the data skew is detected, a multiplexing logic circuitry is used to correct the skew based on one clock cycle either before or after the transition. The multiplexing logic circuitry includes at least three registers coupled to the inputs of the multiplexing logic circuitry.

Method and circuit for de-skewing data in a communication system

A dual-voltage secure digital (SD) card can be inserted into a legacy host or a newer host. Legacy hosts drive a high voltage such as 3.3 volts onto the power line of the SD bus, while newer hosts drive the power line with a reduced voltage such as 1.8 volts. A flash and voltage controller chip on the SD card has a controller core that operates at the reduced voltage. A voltage regulator on the SD card, or a power management unit inside the controller chip generates an internal power voltage of 1.8 volts from the dual-voltage SD bus power line. The internal power voltage is applied to the controller core and to a voltage converter that generates a flash power voltage from the internal power voltage. The flash power voltage is applied to flash-memory chips on the SD card that operate at the higher voltage.

Flash card and controller with integrated voltage converter for attachment to a bus that can operate at either of two power-supply voltages

A cyclic redundancy check (CRC) generator, in accordance with a specific embodiment of the present invention, generates a 32-bit CRC for each packet whose data bytes are carried over a 128-bit bus by first dividing the data bytes by a 123degree generator polynomial and subsequently dividing the remainder of the first division by a 32degree generator polynomial. Data bytes of a new packet are divided by a different dividing logic than those of a current packet. The remainder of division performed on the bytes of a new packet are supplied to the dividing logic adapted to divide the bytes of a current packet. The division by the 123degree generator polynomial is performed on a per byte basis, with the remainder of the division of the (i+1)byte being used in the division of the ibyte.

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Saratoga, CA, United States of America

Chris Tsu