Intel Corporation

Hewlett-packard Development Company, L.p.

Chris Poirier

Krishnakanth Venkata Sistla

Ankush Varma

Eric J DeHaemer

Avinash N Ananthakrishnan

Martin Rowland

Stephen H Gunther

Jeremy J Shrall

Devadatta V Bodas

Hang T Nguyen

Vivek Garg

Matthew M Bace

Xiuting C Man

Thi Dang

Krishna K Rangan

Cyprian W Woo

Ian M Steiner

James Ignowski

Don Soltis

Tessil Thomas

Kevin Safford

Viktor D Vogman

Russell C Brockmann

Sandeep Ahuja

Malini Krishnan Bhandaru

Scott P Bobholz

Brian J Griffith

Robin A Steinbrecher

Susan F Smith

Eric Dehaemer

Joseph R Doucette

Don C Soltis, Jr

Martin Mark T Rowland

Samuel W Ho

Jane Wang

One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

Mechanism to provide workload and configuration-aware deterministic performance for microprocessors

In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.

Adaptive algorithm for thermal throttling of multi-core processors with non-homogeneous performance states

A processor is described having a semiconductor chip having non volatile storage circuitry. The non volatile storage circuitry has information identifying a maximum operational frequency of the processor at which the processor's operation is guaranteed for an ambient temperature that corresponds to an extreme thermal event.

Processor having frequency of operation information for guaranteed operation under high temperature events

A method and apparatus for per core performance states in a processor. Per Core Performance States (PCPS) refer to the parallel operating of individual cores at different voltage and/frequency points. In one embodiment of the invention, the processor has a plurality of processing cores and a power control module that is coupled with each of the plurality of processing cores. The power control module facilitates each processing core to operate at a different performance state from the other processing cores. By allowing its cores to have per core performance state configuration, the processor is able to reduce its power consumption and increase its performance.

Method and apparatus for per core performance states

In an embodiment, a processor includes a core to execute instructions, uncore logic coupled to the core, and a power controller to control a power consumption level. The power controller is configured to determine an activity level of the processor and responsive to this level, to generate a request for communication to a second processor coupled to the processor to request frequency coordination between the processors. Other embodiments are described and claimed.

Performing frequency coordination in a multiprocessor system

In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.

Adaptively limiting a maximum operating frequency in a multicore processor

In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.

Enforcing a power consumption duty cycle in a processor

An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is to store different, appropriate performance related information for different configurations and/or usage cases of the processor for a same performance state of the processor.

A method and apparatus are provided for improving the rate at which macroinstructions are transformed into corresponding microinstructions. Encoding is added to a microcode storage device. The encoding indicates that a microinstruction flow will end in a determined number of cycles. The number of cycles is determined by the number of canceled instructions in a processing pipeline that would be introduced if no flow length prediction was used. For flow lengths less than a determined number of cycles, a hint bit is used in an entry point structure. For flow lengths greater than a determined length, a hint bit is encoded at a third line from an end of the microinstruction flow. Using this method, flows of any length can be hinted. Furthermore, flows that do not originate from the entry point structure can also be hinted. The method reduces the number of hint bits that are needed in the entry point structure and provides for better prediction.

Method and apparatus to reduce penalty of microcode lookup

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Fort Collins, CO, United States of America

Chris Poirier