Advanced Micro Devices Corporation

Chris N Hinds

Paul K Miller

Ashraf Ahmed

Mark A Silla

Mark R Luedtke

A superscalar microprocessor includes a combination floating point and multimedia unit. The floating point and multimedia unit includes one set of registers. The multimedia core and floating point core share the one set of registers. Each register as a type field associated with the register. The type field identifies whether the associated register contains valid data and whether the data is of multimedia type or floating point type. If the register stores floating point type data, the type field further indicates which of a plurality of floating point types the register stores such as: zero, infinity and normal. The floating point core relies on the type field to identify special floating point numbers such as zero and infinity. To ensure predictable results when a floating point instruction is executed subsequent to a multimedia instruction, a retyping algorithm retypes registers typed as multimedia type when the first floating point instruction subsequent to a multimedia instruction is executed. The retyping algorithm reads each register and reclassifies the registers classified as multimedia type. The reclassification algorithm classifies the contents of the register interpreted as floating point data.

Floating point and multimedia unit with data type reclassification

A flip-flop with enhanced support for dynamic circuits. The flip-flop comprises at least one data input node along with at least one inverting and at least one non-inverting output node. A clock input node receives an external clock signal and transmits it to a clocking unit which, in turn, generates a clock signal therefrom for gating an input signal received at the data input node. A storage unit holds the input signal value upon assertion of the clock signal and simultaneously transmits that value in appropriate logic level to inverting and non-inverting outputs. It is understood that the inverting and non-inverting outputs represent complementary signal values as is normally known in the art. The flip-flop further comprises a clear input node which is coupled to an edge-sensitive quiescent state control unit. A predetermined logic state transition, i.e. high to low or low to high, of a control signal applied to the clear input node triggers the edge-sensitive quiescent state control unit which, in turn, drives the inverting and non-inverting nodes to an identical logic level, i.e. either quiescent high or quiescent low depending on the design considerations. A non-inverted output signal and/or an inverted output signal at the inverting and non-inverting nodes, respectively, may be used to control the discharge of a node in a dynamic circuit. Since each of the output signals is cleared to a quiescent state after the signal is applied as an input to the dynamic circuit, the output of the flip-flop will not erroneously cause discharge of the node of the dynamic circuit when the next edge of the clock signal occurs.

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Chris N Hinds