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Urenschi Assets Limited Liability Company

International Business Machines Corporation

Callahan Cellular LLC

Chris Karabatsos

Gary W Smith

Harry Cheselka

Gerald J Hladik

Lawrence G Mosher

Richard M Morrison

An engine comprises one or more cylinders, each cylinder comprising a piston, a connecting rod, a crank shaft, and a crankpin, wherein the crankpin further comprises a main crankpin and a crankpin extension, wherein the connecting rod is affixed at one end to the piston and at another end to a first end of the crankpin extension, wherein a second end of the crankpin extension is affixed to a first end of the main crankpin, and wherein a second end of the main crankpin is affixed to the crankshaft.

Engine crankshaft and method of use

A digital apparatus for phase aligning output signals of a silicon device to an applied input clock signal in same device allows synchronization of data transfers between the device and another device such as a controller. It includes a digital or analog oscillator of higher frequencies than the applied clock and in multiples of powers 2where n=1, 2, 4, etc., with provisions for synchronization and control by the applied input clock. The main oscillator frequency is subdivided to lower frequencies. An internally derived duplicate frequency clock is phase shifted by either 45 or 22.5 degrees. The system measure both a desired coarse delay, and a fine delay to be applied to the path to phase align the output signal to the phase of the applied input clock.

Synchronization of a data output signal to an input clock

A Flash memory system includes N flash devices, where N is an integer, each flash device having a flash device interface consisting of a control signal line, a R/B signal line, and a I/O signal line, and wherein each flash device has an operating speed of s. A logic block is connected to each flash device interface, and is further connected to a controller which whose interfaces also has a control signal line, a R/B signal line, and a I/O signal line, so that controller operates at an operating speed of N times s, and wherein the logic block controls each flash device simultaneously.

High performance data rate system for flash devices

A system for converting the energy created by the ignition of fuel in one or more cylinders of an internal combustion engine to rotational power, having a piston within each of its cylinders, includes one or more first connecting rods, each rotatingly affixed at a first end to the corresponding piston, a master crank to which each such first connecting rod is rotatingly attached at a second, a load crank and one or more second connecting rods, the number corresponding to the number of first connecting rods, each second connecting rod rotatingly affixed at one end to the master crank, and at the other end to the load crank. The second connecting rods may be of the same length as that of the first connecting rods, or of different length.

Four cycle engine with load crank

An Active edge connector for memory modules has a base including two PCB sides and a spacer separating the sides, with driver chips mounted on each side of each side, printed wiring electrically connecting a first set of electrical signals from each of the driver chips to a mother board on which the connector is mounted, and printed wiring for electrically connecting a second set of electrical signals from each of the driver chips to a memory module inserted in the edge connector. When a group of connectors are mounted on a mother board, electrical signals arriving at the first connector are routed to its driver chips, producing re-driven signals to the next connector, and so on. A decoder circuit provides addressing signals determining the last such connector to which the signals are intended, and which prevents the signals from going to any connectors containing memories not addressed.

Active dual in line memory module connector with re-driven propagated signals

A packaging technology for silicon chips is similar to ball grid array packaging technology of the prior art without, however, the use of printed board substrate of the prior art Instead pins are used that are part of a planar frame, the pins folded to a position 90 degrees from the plane of the frame, after which the frame is disposed in contact with the chip, pads on the frame and the chip are connected, and then entire assembly is then encapsulated. The edges of the frame are then cut off, leaving the encapsulation to maintain the configuration of the package in place.

Chip packaging with metal frame pin grid array

A High Frequency Digital Oscillator contains a ring oscillator having an output fn, and having coarse and fine frequency adjustments, wherein the input signal fis the input to both the ring oscillator and the High-Frequency Digital Oscillator, which has a multiplicity of output signals including f, f, and fat one-half, one fourth, and one-eighth the frequency of fn respectively, and wherein an input gating signal causes the oscillator to start or stop, a signal fc=&#xbc;*(f) causing a coarse frequency adjustment and a signal &#x394;=(1/f&#x2212;1/fc) making a fine adjustment, and by stopping the new output before the rising edge of f; and then restarting starting the new output at the rising edge of so that the output and input are synchronized.

High frequency digital oscillator-on-demand with synchronization

A method for synchronizing an output signal of a device phase aligned with an input clock includes the steps of providing an oscillator signal having a period &#x3a0;n of 1/(f*2), wherein fis the clock frequency, and wherein the oscillator signal is phase aligned with the input clock signal, so a multiple of the clock frequency is produced. A number of delayed signals are generated, each having the same period as the input clock signal, but delayed by multiples of one-half the oscillator period from the input clock. The phase difference between the unadjusted output signal each delayed signal is determined, and the smallest value of the phase difference calculated. This smallest phase difference value is then added to the clock signal, resulting in a delayed clock, which is then used to generated the delayed output signal, which will be in close synchronization with the input clock.

Synchronization of a data output signal to a clock input

A High Frequency Digital Oscillator contains a ring oscillator having an output fn, and having coarse and fine frequency adjustments, wherein the input signal fis the input to both the ring oscillator and the High-Frequency Digital Oscillator, which has a multiplicity of output signals including f, f, and fat one-half, one fourth, and one-eighth the frequency of fn respectively, and wherein an input gating signal causes the oscillator to start or stop, a signal fc=1/4*(f) causing a coarse frequency adjustment and a signal A=(1/f&#x2212;1/fc) making a fine adjustment, and by stopping the new output before the rising edge of f; and then restarting starting the new output at the rising edge of so that the output and input are synchronized.

A circuit for terminating devices attached to a signal line and driving a load includes a resistor Rin series with the signal line circuit CRhaving a resistor in series with a switch wherein CRis in parallel with R, a circuit CRhaving a resistor in series with a switch, connected at one end to Vcc and at the other to the load, a circuit CRhaving a resistor in series with a switch, connected at one end to Vcc and at the other to the load, a circuit CRhaving a resistor in series with a switch, connected at one end to ground and at the other to the load, a circuit CRhaving a resistor in series with a switch, connected at one end to Vcc and at the other to the load, and a capacitor connected between the receiver or transmitter and ground.

Growing community of inventors

Kingston, NY, United States of America

Chris Karabatsos