Intel Corporation

Chris J Newburn

Hong Wang

Ittai Anati

Bryant E Bigbee

Dion Rodgers

Xiang Chris Zou

Gilbert A Neiger

Robert P Knight

Milind Baburao Girkar

Gautham N Chinya

Robert Geva

Robert Valentine

Mark Jay Charney

Bret L Toll

Christopher J Hughes

Jesus Corbal

Jason W Brandt

Martin Guy Dixon

Ali-Reza Adl-Tabatabai

Scott Dion Rodgers

Srinivas Chennupaty

James B Crossland

Jonathan Cannon Hall

Rajesh S Parthasarathy

Mark J Buxton

Peter Lachner

Ram Huggahalli

Anwar Ghuloum

Jeffrey G Wiedemeier

Mayank Bomb

Hideki (Saito) Ido

Yen-Kuang (y K) Chen

Simon C Steely, Jr

Baiju V Patel

Per H Hammarlund

John Thomas Shen

Michael Mishaeli

William C Hasenplaugh

Herbert H J Hum

Samantika S Sury

John L Reid

Don Alan Van Dyke

Will Deutsch

Muhammad Faisal Azeem

Wei Ey Li

Darrell D Boggs

Shivnandan D Kaushik

David Sehr

Perry H Wang

John P Shen

Xinmin Tian

Anil Aggarwal

Doron Orenstein

Rajesh R Shah

Larry O Smith

Jim B Crossland

Kumar Shiv

Edward Barragy

Rajesh R Sha

Aaron N Levinson

Richard Grove

Shivanandan Kaushik

A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate a packed data register of the plurality of packed data registers that is to store a source packed memory address information. The source packed memory address information is to include a plurality of memory address information data elements. An execution unit is coupled with the decode unit and the plurality of packed data registers, the execution unit, in response to the instruction, is to load a plurality of data elements from a plurality of memory addresses that are each to correspond to a different one of the plurality of memory address information data elements, and store the plurality of loaded data elements in a destination storage location. The destination storage location does not include a register of the plurality of packed data registers.

Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers

A system according one exemplary embodiment may receive instructions regarding a callee function that include a description of properties associated with arguments for the callee function, create a persistent representation of the callee function based on the received description of the callee function, receive instructions from a source describing a set of properties for a data collection, create a persistent representation of the data collection based on the set of properties for the data collection, receive an updated property for the data collection, and in response to receiving the updated property for the data collection: update the persistent representation of the callee function by associating the persistent representation of the callee function with the updated property of the data collection and update the persistent representation of the data collection by associating the persistent representation the data collection with the updated property of the data collection.

Declarative properties for data collections

A system according to an exemplary embodiment receives an operand descriptor identifying characteristics of a set of data elements referenced by an operand to be accessed from a set of locations in a memory, wherein the operand descriptor describes an ordering of the set of data elements and respective locations in the memory for each respective data element in the set of data elements. The system further accesses the set of data elements in the memory based on the operand descriptor.

Memory operand descriptors

A system according to an exemplary embodiment receives a description of a first set of data elements referenced in a first operand, receives a description of a second set of data elements referenced in a second operand, selects a set of subsets of data elements that are included in both the first set of data elements and the second set of data elements, wherein selecting the set of subsets of data elements includes optimizing a size of the set of subsets of data elements, provides the set of subsets of data elements, and in response to a reference by the second operand that modifies the set of subsets of data elements, provides a respective mapping from each previous subset in the set of subsets to a respective new collection of subsets in the set of subsets.

Multi-grained memory operands

An exemplary system according to various examples receives a function call including a plurality of operands, each operand in the plurality of operands comprising a set of data elements. The system identifies a plurality of actions associated with the function call and the plurality of operands, determines a set of dependencies among the plurality of actions for executing the actions using a set of computing resources, and presents the set of actions and the determined set of dependencies.

Task mapping for heterogeneous platforms

According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

Gathering and scattering multiple data elements

A system according to one exemplary embodiment comprises: a processor; and memory coupled to the processor and storing instructions that, when executed by the processor, cause the system to: receive, by a software component operating on the system: a set of actions, an identification of a set of computing resources to associate with the set of actions, and a set of dependencies among the plurality of actions for executing the actions using the computing resources; associate the set of actions and data elements related to the set of actions, by the software component, with the set of computing resources; and order, by the software component, each respective action in the set of actions for execution on the computing resources.

Flexible binding of tasks to target resources

Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.

System to profile and optimize user software in a managed run-time environment

Method, apparatus, and system for a programmable event-driven yield mechanism. The mechanism may disrupt processing of a program to deliver a yield event. The event may be treated as a fault-like yield event or a trap-like event. For a fault-like yield event, the faulting instruction is canceled before retirement and processor state is not updated before the yield event is delivered. For a trap-like yield event the instruction causing the trap is retired and the yield event is delivered on an interrupt boundary. Multiple pending yield events may be handled according to priority. Other embodiments are also described and claimed.

Programmable event-driven yield mechanism

Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.

Context state management for processor feature sets

Growing community of inventors

South Beloit, IL, United States of America

Chris J Newburn