Topside Research, LLC

Internet Machines Corp.

Other

Rambus Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Chris Haywood

Heath Stewart

Michael J De La Garrigue

Thomas C Reiner

Ken Wong

Adam Rappoport

Bao K Vuong

Nadim Shaikli

Phil Terry

Kirk Jong

Neely Walls

Mike De La Garrigue

There is disclosed apparatus and methods of multicasting in a shared address space. A shared memory address space may include two or more multicast portions. Each multicast portion may be associated with a respective end point and with at least one other multicast portion. Data units may be transmitted to at least some of the end points via memory-mapped I/O into the shared memory address space. When a destination address of a data unit is in a first multicast portion associated with a first end point, the data unit may be transmitted to the first end point, revised to specify a destination address in a second multicast portion associated with the first multicast portion, and transmitted to a second end point associated with the second multicast portion.

Multicasting computer bus switch

A memory load sharing system and method therefor. This system can include a platform VRM (Voltage Regulator Module) coupled to a memory channel with the platform VRM having a platform voltage input. One or more first memory modules can coupled to the platform VRM through the memory channel. Each of the first memory modules includes one or more plane connectors and a module connector, as well as a memory module VRM coupled to a module load sharing diode that is coupled to the one or more plane connectors of that first memory module. The platform VRM is coupled to a first platform load sharing diode that is coupled the plane connectors of each of the first memory modules. This platform is configured to support load sharing between the first memory modules and to provide a predetermined amount of power to each of the memory modules.

Method and system using memory channel load sharing

A network processor having bypass capability in which some data units are diverted from being processed by the processor core of the network processor. In one embodiment, a network processor may include a receiver to receive data units, configuration information used to evaluate whether the data units require processing, a processor core to process data units that require processing, a bypass store to hold those data units which do not require processing by the processor core, and a transmitter to transmit the data units. In one embodiment, a method may include receiving a plurality of data units, receiving configuration information, evaluating whether each of the data units requires processing based on the configuration information, bypassing processing those of the data units that do not require processing based on the evaluating, processing those of the data units that require processing based on the evaluating, and transmitting the data units.

Network processor having bypass capability

Methods for routing data units and PCI Express switches are disclosed. A plurality of devices may be coupled to a corresponding plurality of physical interfaces, each physical interface having a respective configurable status and a respective address domain, wherein in a first status the interface is transparent, and in a second status the interface is non-transparent. The status of each of the plurality of physical interfaces may be set as transparent or non-transparent. Data units may be switched between the physical interfaces using mapped address input/output, switching data units including masking the address domain for the interfaces configured as non-transparent.

Routing data units between different address domains

There are disclosed apparatus and methods for switching. Transparent and non-transparent ports are provided. Data units are transferred between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports.

PCI express switch with backwards compatibility

A variable size first in first out (FIFO) memory is disclosed. The variable size FIFO memory may include head and tail FIFO memories operating at a very high data rate and an off chip buffer memory. The off chip buffer memory may be, for example, of a dynamic RAM type. The off chip buffer memory may temporarily store data packets when both head and tail FIFO memories are full. Data blocks of each of the memories may be the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head and tail FIFO memories return to their initial functions with the head FIFO memory directly receiving high speed data and transmitting it to various switching element and the tail FIFO memory storing temporary overflows of data from the head FIFO memory.

Variable size FIFO memory

There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.

Optimized switching method

There is disclosed apparatus and methods of multicasting in a shared address space. There may be defined a number of portions of the address space. There may be groups of the portions, and data units addressed to one portion within the group may be re-addressed to the other portions.

Multicasting in a shared address space

Switch with transparent and non-transparent ports

Switch for bus optimization

Switching with transparent and non-transparent ports

A variable size first in first out (FIFO) memory is provided. The variable size FIFO memory may include head and tail FIFO memories operating at a very high data rate and an off chip buffer memory. The off chip buffer memory may be, for example, of a dynamic RAM type. The off chip buffer memory may temporarily store data packets when both head and tail FIFO memories are full. Data blocks of each of the memories may be the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head and tail FIFO memories return to their initial functions with the head FIFO memory directly receiving high speed data and transmitting it to various switching element and the tail FIFO memory storing temporary overflows of data from the head FIFO memory.

Variable size First In First Out (FIFO) memory with head and tail caching

A head and tail caching system. The system includes a tail FIFO memory having a tail input to receive incoming data. A memory is included that is operable to store data that is output from the tail FIFO and output the stored data at a memory output. A multiplexer is included having first and second multiplexer inputs coupled to the tail FIFO and the memory, respectively. The multiplexer has a control input to select one of the multiplexer inputs to coupled to a multiplexer output. A head FIFO memory receives data from the multiplexer output, and outputs the data on an output data path. A controller is operable to transfer one or more blocks data having a selected block size from the tail FIFO to the memory and from the memory to the head FIFO, to achieve a selected efficiency level.

Growing community of inventors

Thousand Oaks, CA, United States of America

Chris Haywood