Micron Technology Incorporated

Other

Round Rock Research, LLC

Chris G Martin

Troy A Manning

Brent Keeth

Stephen L Casper

Brian L Johnson

Shubneesh Batra

David J Corisis

Timothy B Cowles

Paul A LaBerge

Joe M Jeddeloh

Manny Kin F Ma

Jim Rehmeyer

Charles H Dennison

Walter L Moden

Brian M Shirley

James Brian Johnson

Jeffery W Janzen

Brian L Brown

Ming-Bo Liu

Jeffrey W Janzen

Christopher B Cooper

Salman Akram

Todd A Merritt

Manny K Ma

Michael D Chaine

Ebrahim H Hargan

Eric J Smith

Terry R Lee

Donald M Morgan

Kevin J Ryan

Thomas W Voshell

Wallace E Fister

Kim M Pierce

Mike Pearson

Jeff Irwin

Jeff Crawford

Tammy Martin

An exercise device comprising an outer tube having a first end and an open second end. An inner tube has a first end fitting inside the open second end of the outer tube. Thus, the inner tube can slide inside the outer tube. Typically, from about 5 percent to about 30 percent of the inner tube will be inside the outer tube when the device is at rest (that is, no force is applied). When the user applies a force to the first end of the outer tube, the inner tube can slide inside the outer tube against force provided by a resistance device. Depending on the force applied, the inner tube can be inserted from about 10 percent to about 100 percent of its length inside the outer tube. The resistance device can be a spring, an elastic cord, magnetic repulsion, or the like.

Portable oblique, abdominal and core exercising device

An apparatus for the preparation of comestible-containing sandwich products comprises a sandwich product assembly station and corresponding means for the fabrication and assembly of a sandwich product in the vertical direction. The apparatus includes an extruder nozzle, wafer trays and corresponding components for the location of wafers on opposite sides of the extruded product, an indexing wheel for receiving the assembled sandwich product, and sandwich transporting means for moving the sandwich to a wrapping assembly and from there to a discharge end, wherein all of the components of the apparatus are mounted in cantilevered fashion on a vertical support or base member. Each element is powered individually by a servo motor or actuator and controlled by a controller allowing the variability of throughput for each station.

Servo driven ice cream sandwich assembly and wrapping machine

Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.

Stacked device remapping and repair

A skin topical applicator apparatus includes an arm that has a first end and a second end. A cavity is positioned in the arm and is adjacent to the first end. A mount is attached to the arm and extends away from the first end of the arm. A roller is rotatably attached to the mount. A canister is removably mounted in the cavity and a nozzle is fluidly coupled to the canister and extends outwardly of the first end. The nozzle is directed toward the roller. The canister is filled with a fluid under pressure. The canister includes a valve that is actuated to release the fluid into the nozzle to coat the roller with the fluid.

Skin topical applicator apparatus

An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Active termination circuit and method for controlling the impedance of external integrated circuit terminals

An apparatus that indicates the speed of oncoming trains at train crossings comprises a large digital display attached to a drop gate or alternately on a side gate crossing sign for those crossings without a gate. The digital display is surrounded by a large sign indicating the speed of an oncoming train. A speed detection device aimed in either direction on the track to determine train speed. An interface converts the detected speed into a digital display. It is envisioned that motorists knowing the speed of an oncoming train will be less likely to try to beat the train through the crossing.

Speedometer for train crossings

Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.

An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

Apparatus and method for repairing a semiconductor memory

An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

On-chip sampling circuit and method

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Boise, ID, United States of America

Chris G Martin