Micron Technology Incorporated

Motorola Corporation

Micron Semiconductor, Inc.

Chris C Yu

Gurtej S Sandhu

Trung Tri Doan

Tat-Kwan Edgar Yu

Karl M Robinson

Jeffrey L Klein

Tyler A Lowrey

David A Cathey

Terry L Gilton

J Brett Rolfson

Papu D Maniar

Sung C Kim

Alan E Laulusa

Jeffrey F Hanson

A method for depositing metal on a semiconductor device having a substrate, an exposed first surface, and an exposed second surface is provided. Metal ions are deposited on the exposed first surface and on the exposed second layer by applying a first voltage between the substrate and an anode in the presence of an electrolytic bath, and metal ions are removed from the exposed first surface by applying a second voltage between the substrate and the anode in the presence of the electrolytic bath. Other aspects and embodiments are provided herein.

Method for forming a metallization layer

A method for forming a metallization layer. A first layer is formed outwardly from a semiconductor substrate. Contact vias are formed through the first layer to the semiconductor substrate. A second layer is formed outwardly from the first layer. Portions of the second layer are selectively removed such that the remaining portion of the second layer defines the layout of the metallization layer and the contact vias. The first and second layers are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer. Further, metal ions deposited on the first layer during a positive duty cycle are removed from the first layer during a negative duty cycle. Finally, exposed portions of the first layer are selectively removed.

Semiconductor manufacturing system for forming metallization layer

A method for forming a metallization layer (). A first layer () is formed outwardly from a semiconductor substrate (). Contact vias () are formed through the first layer () to the semiconductor substrate (). A second layer () is formed outwardly from the first layer (). Portions of the second layer () are selectively removed such that the remaining portion of the second layer () defines the layout of the metallization layer () and the contact vias (). The first and second layers () and () are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer (). Further, metal ions deposited on the first layer () during a positive duty cycle are removed from the first layer () during a negative duty cycle. Finally, exposed portions of the first layer () are selectively removed.

A method for forming conductive plugs within an insulation material is described. The inventive process results in a plug of a material such as tungsten which is more even with the insulation layer surface than conventional plug formation techniques. Conventional processes result in recessed plugs which are not easily or reliably coupled with subsequent layers of sputtered aluminum or other conductors. The inventive process uses a two-step chemical mechanical planarization technique. An insulation layer with contact holes is formed, and a metal layer is formed thereover. A polishing pad rotates against the wafer surface while a slurry selective to the metal removes the metal overlying the wafer surface, and also recesses the metal within the contact holes due to the chemical nature and fibrous element of the polishing pad. A second CMP step uses a slurry having an acid or base selective to the insulation material to remove the insulator from around the metal. The slurry also contains abrasive materials which polish the metal surface so as to make the metal level with the insulation layer surface. Removal of the insulation material can continue, thereby producing a slightly protruding plug which results in a more reliable contact from the substrate to subsequent conductive layers.

Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs

The present invention is a semiconductor wafer, and a method of fabricating the semiconductor wafer, that reduces dishing over large area features in chemical-mechanical polishing processes. The semiconductor wafer has a substrate with an upper surface, a large area feature formed on the substrate, and a separation layer deposited on the substrate. The separation layer has a top surface and a cavity extending from the top surface towards the upper surface of the substrate. The large area feature is positioned in the cavity of the separation layer, and a support pillar is positioned in the cavity. In one embodiment, the pillar has a base positioned between components of the large area feature and a crown positioned proximate to a plane defined by the top surface of the separation layer. In operation, the pillar substantially prevents the polishing pad of a polishing machine from penetrating into the cavity beyond the top surface of the separation layer.

Semiconductor wafer for improved chemical-mechanical polishing over large area features

An apparatus and method for uniformly planarizing a surface of a semiconductor wafer and accurately stopping CMP processing at a desired endpoint. In one embodiment, a planarizing machine has a platen mounted to a support structure, an underpad attached to the platen, a polishing pad attached to the underpad, and a wafer carrier assembly. The wafer carrier assembly has a chuck with a mounting cavity in which the wafer may be mounted, and the wafer carrier assembly moves the chuck to engage a front face of the wafer with the planarizing surface of the polishing pad. The chuck and/or the platen moves with respect to the other to impart relative motion between the wafer and the polishing pad. The planarizing machine also includes a pressure sensor positioned to measure the pressure at an area of the wafer as the platen and the chuck move with respect to each other and while the wafer engages the planarizing surface of the polishing pad. The pressure sensor generates a signal in response to the measured pressure that corresponds to a planarizing parameter of the wafer. In a preferred embodiment, the planarizing machine further includes a converter operatively connected to the pressure sensor, a controller operatively connected to the converter, and a plurality of drivers operatively connected to the controller and positioned in the mounting cavity.

Chemical-mechanical planarization machine and method for uniformly planarizing semiconductor wafers

A method for forming a metallization layer (,). A first layer (,) is formed outwardly from a semiconductor substrate (,). Contact vias (,) are formed through the first layer (,) to the semiconductor substrate (,). A second layer (,) is formed outwardly from the first layer (,). Portions of the second layer (,) are selectively removed such that the remaining portion of the second layer (,) defines the layout of the metallization layer (,) and the contact vias (,). The first and second layers (,) and (,) are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer (,). Further, metal ions deposited on the first layer (,) during a positive duty cycle are removed from the first layer (,) during a negative duty cycle. Finally, exposed portions of the first layer (,) are selectively removed.

Methods of forming metallization layers and integrated circuits containing such

Chemical-mechanical planarization machine and method for uniformly

An integrated circuit includes a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through the first layer (14) to the semiconductor substrate (10). A second layer (20) is formed outwardly from the first layer (14). Portions of the second layer (20) are selectively removed such that the remaining portion of the second layer (20) defines the layout of the metallization layer (30) and the contact vias (16). The first and second layers (14) and (20) are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer (20). Further, metal ions deposited on the first layer (14) during a positive duty cycle are removed from the first layer (14) during a negative duty cycle. Finally, exposed portions of the firs layer (14) are selectively removed.

Metallization layer

Conductive plugs (28) are formed in a semiconductor device (10) using a chemical mechanical polishing (CMP) process. A blanket conductive layer (26), for example of tungsten, is deposited in a plug opening (24). The conductive layer is polished back by CMP using a slurry comprised of either copper sulfate (CuSO.sub.4) or copper perchlorate [Cu(ClO.sub.4).sub.2 ] and an abrasive, such as alumina or silica, and water. In another embodiment, a CMP process using such slurries may be used to form conductive interconnects (50) in a semiconductor device (40).

Method for chemical mechanical polishing a semiconductor device using

The present invention includes a polishing pad to improve polishing uniformity across a semiconductor substrate and a method using the polishing pad. The polishing pad has a first region that is closer to the edge of the polishing pad and a second region adjacent to the first region and further from the edge of the polishing pad. The polishing pad is configured, so that the second region is thicker or less compressible compared to the first region. The polishing pad should not require significantly changing any of the equipment. Oscillating range and possibly polishing pressure may need to be changed when one of the polishing pads of the present invention is used. Other operational parameters are not expected to be substantially different from a conventional polishing pad, although slight optimization of the other operating parameters may be needed.

Polishing pad for chemical-mechanical polishing of a semiconductor

Semiconductor wafer for improved chemical-mechanical polishing over

The present invention includes a modified polishing pad and methods on how to form and use the polishing pad. In one embodiment, a modified polishing pad is formed similar to polishing substrates except that the modifying pressure should be large enough to mechanically deform part of the polishing pad. The modifying pressure is typically at least 10 pounds per square inch. The materials used to modify the pad should be hard with a smooth surface. Examples of these materials are metals, dielectrics, and semiconductors. After modifying the polishing pad, it may be used to polish semiconductor substrates. Compared to a fresh pad, the modified polishing pad should have a higher planarization efficiency and be less likely to cause corner rounding of a patterned layer adjacent to an opening.

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Austin, TX, United States of America

Chris C Yu